radv: add GFX9 support for color surfaces.
This is ported from radeonsi. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -902,21 +902,44 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
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struct radv_color_buffer_info *cb)
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{
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bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
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radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
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radeon_emit(cmd_buffer->cs, cb->cb_color_base);
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radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
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radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
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radeon_emit(cmd_buffer->cs, cb->cb_color_view);
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radeon_emit(cmd_buffer->cs, cb->cb_color_info);
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radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
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radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
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radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
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radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
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radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
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radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
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if (is_vi) { /* DCC BASE */
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radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
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if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
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radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
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radeon_emit(cmd_buffer->cs, cb->cb_color_base);
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radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
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radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
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radeon_emit(cmd_buffer->cs, cb->cb_color_view);
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radeon_emit(cmd_buffer->cs, cb->cb_color_info);
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radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
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radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
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radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
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radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
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radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
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radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
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radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
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radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
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radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
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radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
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cb->gfx9_epitch);
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} else {
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radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
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radeon_emit(cmd_buffer->cs, cb->cb_color_base);
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radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
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radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
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radeon_emit(cmd_buffer->cs, cb->cb_color_view);
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radeon_emit(cmd_buffer->cs, cb->cb_color_info);
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radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
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radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
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radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
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radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
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radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
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radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
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if (is_vi) { /* DCC BASE */
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radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
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}
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}
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}
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@ -2703,7 +2703,20 @@ radv_initialise_color_surface(struct radv_device *device,
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va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
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{
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if (device->physical_device->rad_info.chip_class >= GFX9) {
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struct gfx9_surf_meta_flags meta;
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if (iview->image->dcc_offset)
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meta = iview->image->surface.u.gfx9.dcc;
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else
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meta = iview->image->surface.u.gfx9.cmask;
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cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
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S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
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S_028C74_RB_ALIGNED(meta.rb_aligned) |
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S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
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va += iview->image->surface.u.gfx9.surf_offset >> 8;
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} else {
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const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
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unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
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@ -2835,6 +2848,21 @@ radv_initialise_color_surface(struct radv_device *device,
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unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
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cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
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}
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if (device->physical_device->rad_info.chip_class >= GFX9) {
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uint32_t max_slice = radv_surface_layer_count(iview);
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unsigned mip0_depth = iview->base_layer + max_slice - 1;
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cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
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cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
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S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
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cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->image->info.width - 1) |
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S_028C68_MIP0_HEIGHT(iview->image->info.height - 1) |
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S_028C68_MAX_MIP(iview->image->info.levels);
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cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
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}
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}
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static void
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@ -1342,12 +1342,14 @@ struct radv_color_buffer_info {
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uint32_t cb_color_view;
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uint32_t cb_color_info;
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uint32_t cb_color_attrib;
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uint32_t cb_color_attrib2;
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uint32_t cb_dcc_control;
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uint32_t cb_color_cmask_slice;
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uint32_t cb_color_fmask_slice;
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uint32_t cb_clear_value0;
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uint32_t cb_clear_value1;
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uint32_t micro_tile_mode;
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uint32_t gfx9_epitch;
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};
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struct radv_ds_buffer_info {
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