i965/vs: Add support for ir_binop_pow.
Fixes vs-pow-float-float.
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250770b74d
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abf843a797
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@ -444,12 +444,22 @@ public:
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void generate_vs_instruction(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg *src);
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void generate_math1_gen4(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src);
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void generate_math1_gen6(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src);
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void generate_math2_gen4(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src0,
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struct brw_reg src1);
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void generate_math2_gen6(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src0,
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struct brw_reg src1);
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void generate_urb_write(vec4_instruction *inst);
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void generate_oword_dual_block_offsets(struct brw_reg m1,
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struct brw_reg index);
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@ -245,6 +245,15 @@ vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
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BRW_MATH_PRECISION_FULL);
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}
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static void
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check_gen6_math_src_arg(struct brw_reg src)
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{
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/* Source swizzles are ignored. */
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assert(!src.abs);
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assert(!src.negate);
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assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW);
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}
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void
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vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
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struct brw_reg dst,
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@ -252,10 +261,7 @@ vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
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{
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/* Can't do writemask because math can't be align16. */
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assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
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/* Source swizzles are ignored. */
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assert(!src.abs);
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assert(!src.negate);
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assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW);
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check_gen6_math_src_arg(src);
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brw_set_access_mode(p, BRW_ALIGN_1);
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brw_math(p,
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@ -269,6 +275,49 @@ vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
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brw_set_access_mode(p, BRW_ALIGN_16);
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}
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void
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vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src0,
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struct brw_reg src1)
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{
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/* Can't do writemask because math can't be align16. */
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assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
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/* Source swizzles are ignored. */
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check_gen6_math_src_arg(src0);
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check_gen6_math_src_arg(src1);
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brw_set_access_mode(p, BRW_ALIGN_1);
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brw_math2(p,
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dst,
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brw_math_function(inst->opcode),
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src0, src1);
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brw_set_access_mode(p, BRW_ALIGN_16);
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}
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void
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vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src0,
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struct brw_reg src1)
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{
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/* Can't do writemask because math can't be align16. */
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assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
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brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src1);
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brw_set_access_mode(p, BRW_ALIGN_1);
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brw_math(p,
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dst,
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brw_math_function(inst->opcode),
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BRW_MATH_SATURATE_NONE,
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inst->base_mrf,
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src0,
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BRW_MATH_DATA_VECTOR,
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BRW_MATH_PRECISION_FULL);
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brw_set_access_mode(p, BRW_ALIGN_16);
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}
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void
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vec4_visitor::generate_urb_write(vec4_instruction *inst)
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{
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@ -442,7 +491,11 @@ vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
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break;
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case SHADER_OPCODE_POW:
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assert(!"finishme");
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if (intel->gen >= 6) {
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generate_math2_gen6(inst, dst, src[0], src[1]);
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} else {
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generate_math2_gen4(inst, dst, src[0], src[1]);
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}
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break;
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case VS_OPCODE_URB_WRITE:
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@ -188,11 +188,11 @@ vec4_visitor::emit_math2_gen6(enum opcode opcode,
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*/
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expanded = src_reg(this, glsl_type::vec4_type);
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emit(BRW_OPCODE_MOV, dst, src0);
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emit(BRW_OPCODE_MOV, dst_reg(expanded), src0);
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src0 = expanded;
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expanded = src_reg(this, glsl_type::vec4_type);
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emit(BRW_OPCODE_MOV, dst, src1);
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emit(BRW_OPCODE_MOV, dst_reg(expanded), src1);
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src1 = expanded;
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if (dst.writemask != WRITEMASK_XYZW) {
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