ac/surface: add displayable DCC code for gfx10.3
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
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@ -1071,8 +1071,12 @@ ASSERTED static bool is_dcc_supported_by_L2(const struct radeon_info *info,
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surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B);
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surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B);
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}
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}
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unreachable("unhandled chip");
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/* 128B is recommended, but 64B can be set too if needed for 4K by DCN.
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return false;
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* Since there is no reason to ever disable 128B, require it.
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* DCC image stores are always supported.
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*/
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return surf->u.gfx9.dcc.independent_128B_blocks &&
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surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
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}
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}
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static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
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static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
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@ -1103,11 +1107,14 @@ static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
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surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
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surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
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return true;
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return true;
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case GFX10:
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case GFX10:
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/* DCN requires INDEPENDENT_128B_BLOCKS = 0.
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case GFX10_3:
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* For 4K, it also requires INDEPENDENT_64B_BLOCKS = 1.
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/* DCN requires INDEPENDENT_128B_BLOCKS = 0 only on Navi1x. */
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*/
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if (info->chip_class == GFX10 &&
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return !surf->u.gfx9.dcc.independent_128B_blocks &&
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surf->u.gfx9.dcc.independent_128B_blocks)
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((config->info.width <= 2560 &&
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return false;
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/* For 4K, DCN requires INDEPENDENT_64B_BLOCKS = 1. */
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return ((config->info.width <= 2560 &&
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config->info.height <= 2560) ||
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config->info.height <= 2560) ||
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(surf->u.gfx9.dcc.independent_64B_blocks &&
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(surf->u.gfx9.dcc.independent_64B_blocks &&
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surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B));
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surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B));
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@ -1655,6 +1662,12 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
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surf->u.gfx9.dcc.independent_128B_blocks = 0;
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surf->u.gfx9.dcc.independent_128B_blocks = 0;
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surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
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surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
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}
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}
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if (info->chip_class >= GFX10_3) {
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surf->u.gfx9.dcc.independent_64B_blocks = 1;
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surf->u.gfx9.dcc.independent_128B_blocks = 1;
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surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
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}
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}
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}
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}
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}
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