intel/fs: Rework fs_inst::is_copy_payload() into multiple classification helpers.
This reworks the current fs_inst::is_copy_payload() method into a number of classification helpers with well-defined semantics. This will be useful later on in order to optimize LOAD_PAYLOAD instructions more aggressively in cases where we can determine it's safe to do so. The closest equivalent of the present fs_inst::is_copy_payload() method is the is_coalescing_payload() helper introduced here. No functional nor shader-db changes. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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@ -427,34 +427,6 @@ fs_inst::has_source_and_destination_hazard() const
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}
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}
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bool
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fs_inst::is_copy_payload(const brw::simple_allocator &grf_alloc) const
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{
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if (this->opcode != SHADER_OPCODE_LOAD_PAYLOAD)
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return false;
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fs_reg reg = this->src[0];
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if (reg.file != VGRF || reg.offset != 0 || reg.stride != 1)
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return false;
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if (grf_alloc.sizes[reg.nr] * REG_SIZE != this->size_written)
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return false;
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for (int i = 0; i < this->sources; i++) {
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reg.type = this->src[i].type;
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if (!this->src[i].equals(reg))
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return false;
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if (i < this->header_size) {
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reg.offset += REG_SIZE;
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} else {
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reg = horiz_offset(reg, this->exec_size);
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}
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}
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return true;
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}
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bool
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fs_inst::can_do_source_mods(const struct gen_device_info *devinfo) const
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{
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@ -105,7 +105,7 @@ is_expression(const fs_visitor *v, const fs_inst *const inst)
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case SHADER_OPCODE_COS:
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return inst->mlen < 2;
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case SHADER_OPCODE_LOAD_PAYLOAD:
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return !inst->is_copy_payload(v->alloc);
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return !is_coalescing_payload(v->alloc, inst);
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default:
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return inst->is_send_from_grf() && !inst->has_side_effects() &&
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!inst->is_volatile();
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@ -86,7 +86,7 @@ is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst)
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return false;
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if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
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if (!inst->is_copy_payload(v->alloc)) {
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if (!is_coalescing_payload(v->alloc, inst)) {
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return false;
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}
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}
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@ -350,7 +350,6 @@ public:
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bool is_send_from_grf() const;
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bool is_payload(unsigned arg) const;
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bool is_partial_write() const;
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bool is_copy_payload(const brw::simple_allocator &grf_alloc) const;
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unsigned components_read(unsigned i) const;
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unsigned size_read(int arg) const;
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bool can_do_source_mods(const struct gen_device_info *devinfo) const;
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@ -570,4 +569,103 @@ has_dst_aligned_region_restriction(const gen_device_info *devinfo,
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return false;
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}
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/**
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* Return whether the LOAD_PAYLOAD instruction is a plain copy of bits from
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* the specified register file into a VGRF.
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*
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* This implies identity register regions without any source-destination
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* overlap, but otherwise has no implications on the location of sources and
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* destination in the register file: Gathering any number of portions from
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* multiple virtual registers in any order is allowed.
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*/
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inline bool
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is_copy_payload(brw_reg_file file, const fs_inst *inst)
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{
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if (inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD ||
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inst->is_partial_write() || inst->saturate ||
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inst->dst.file != VGRF)
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return false;
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for (unsigned i = 0; i < inst->sources; i++) {
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if (inst->src[i].file != file ||
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inst->src[i].abs || inst->src[i].negate)
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return false;
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if (!inst->src[i].is_contiguous())
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return false;
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if (regions_overlap(inst->dst, inst->size_written,
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inst->src[i], inst->size_read(i)))
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return false;
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}
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return true;
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}
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/**
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* Like is_copy_payload(), but the instruction is required to copy a single
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* contiguous block of registers from the given register file into the
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* destination without any reordering.
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*/
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inline bool
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is_identity_payload(brw_reg_file file, const fs_inst *inst) {
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if (is_copy_payload(file, inst)) {
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fs_reg reg = inst->src[0];
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for (unsigned i = 0; i < inst->sources; i++) {
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reg.type = inst->src[i].type;
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if (!inst->src[i].equals(reg))
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return false;
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reg = byte_offset(reg, inst->size_read(i));
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}
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return true;
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} else {
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return false;
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}
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}
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/**
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* Like is_copy_payload(), but the instruction is required to source data from
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* at least two disjoint VGRFs.
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*
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* This doesn't necessarily rule out the elimination of this instruction
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* through register coalescing, but due to limitations of the register
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* coalesce pass it might be impossible to do so directly until a later stage,
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* when the LOAD_PAYLOAD instruction is unrolled into a sequence of MOV
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* instructions.
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*/
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inline bool
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is_multi_copy_payload(const fs_inst *inst) {
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if (is_copy_payload(VGRF, inst)) {
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for (unsigned i = 0; i < inst->sources; i++) {
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if (inst->src[i].nr != inst->src[0].nr)
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return true;
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}
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}
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return false;
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}
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/**
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* Like is_identity_payload(), but the instruction is required to copy the
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* whole contents of a single VGRF into the destination.
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*
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* This means that there is a good chance that the instruction will be
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* eliminated through register coalescing, but it's neither a necessary nor a
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* sufficient condition for that to happen -- E.g. consider the case where
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* source and destination registers diverge due to other instructions in the
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* program overwriting part of their contents, which isn't something we can
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* predict up front based on a cheap strictly local test of the copy
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* instruction.
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*/
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inline bool
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is_coalescing_payload(const brw::simple_allocator &alloc, const fs_inst *inst)
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{
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return is_identity_payload(VGRF, inst) &&
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inst->src[0].offset == 0 &&
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alloc.sizes[inst->src[0].nr] * REG_SIZE == inst->size_written;
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}
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#endif
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