vc4: Restructure depth input/output in fragment shaders.
The goal here is to have an argument for the depth write opcode so that I can do computed depth. In the process, this makes the calculations that will be emitted more obvious in the QIR.
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@ -831,7 +831,7 @@ emit_fragcoord_input(struct vc4_compile *c, int attr)
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c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
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c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
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c->inputs[attr * 4 + 2] =
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c->inputs[attr * 4 + 2] =
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qir_FMUL(c,
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qir_FMUL(c,
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qir_FRAG_Z(c),
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qir_ITOF(c, qir_FRAG_Z(c)),
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qir_uniform_f(c, 1.0 / 0xffffff));
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qir_uniform_f(c, 1.0 / 0xffffff));
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c->inputs[attr * 4 + 3] = qir_FRAG_RCP_W(c);
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c->inputs[attr * 4 + 3] = qir_FRAG_RCP_W(c);
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}
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}
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@ -1238,8 +1238,7 @@ emit_frag_end(struct vc4_compile *c)
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qir_TLB_DISCARD_SETUP(c, c->discard);
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qir_TLB_DISCARD_SETUP(c, c->discard);
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if (c->fs_key->depth_enabled) {
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if (c->fs_key->depth_enabled) {
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qir_emit(c, qir_inst(QOP_TLB_PASSTHROUGH_Z_WRITE, c->undef,
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qir_TLB_Z_WRITE(c, qir_FRAG_Z(c));
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c->undef, c->undef));
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}
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}
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bool color_written = false;
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bool color_written = false;
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@ -77,7 +77,7 @@ static const struct qir_op_info qir_op_info[] = {
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[QOP_VPM_WRITE] = { "vpm_write", 0, 1, true },
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[QOP_VPM_WRITE] = { "vpm_write", 0, 1, true },
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[QOP_VPM_READ] = { "vpm_read", 0, 1, true },
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[QOP_VPM_READ] = { "vpm_read", 0, 1, true },
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[QOP_TLB_DISCARD_SETUP] = { "discard", 0, 1, true },
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[QOP_TLB_DISCARD_SETUP] = { "discard", 0, 1, true },
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[QOP_TLB_PASSTHROUGH_Z_WRITE] = { "tlb_passthrough_z", 0, 0, true },
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[QOP_TLB_Z_WRITE] = { "tlb_z", 0, 1, true },
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[QOP_TLB_COLOR_WRITE] = { "tlb_color", 0, 1, true },
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[QOP_TLB_COLOR_WRITE] = { "tlb_color", 0, 1, true },
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[QOP_TLB_COLOR_READ] = { "tlb_color_read", 1, 0, true },
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[QOP_TLB_COLOR_READ] = { "tlb_color_read", 1, 0, true },
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[QOP_VARY_ADD_C] = { "vary_add_c", 1, 1 },
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[QOP_VARY_ADD_C] = { "vary_add_c", 1, 1 },
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@ -97,7 +97,7 @@ enum qop {
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QOP_VPM_WRITE,
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QOP_VPM_WRITE,
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QOP_VPM_READ,
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QOP_VPM_READ,
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QOP_TLB_DISCARD_SETUP,
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QOP_TLB_DISCARD_SETUP,
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QOP_TLB_PASSTHROUGH_Z_WRITE,
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QOP_TLB_Z_WRITE,
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QOP_TLB_COLOR_WRITE,
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QOP_TLB_COLOR_WRITE,
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QOP_TLB_COLOR_READ,
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QOP_TLB_COLOR_READ,
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QOP_VARY_ADD_C,
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QOP_VARY_ADD_C,
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@ -361,6 +361,7 @@ QIR_ALU0(FRAG_Z)
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QIR_ALU0(FRAG_RCP_W)
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QIR_ALU0(FRAG_RCP_W)
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QIR_ALU0(TEX_RESULT)
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QIR_ALU0(TEX_RESULT)
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QIR_ALU0(TLB_COLOR_READ)
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QIR_ALU0(TLB_COLOR_READ)
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QIR_NODST_1(TLB_Z_WRITE)
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QIR_NODST_1(TLB_DISCARD_SETUP)
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QIR_NODST_1(TLB_DISCARD_SETUP)
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static inline struct qreg
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static inline struct qreg
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@ -243,8 +243,7 @@ vc4_generate_code(struct vc4_compile *c)
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if (qinst->src[i].file == QFILE_TEMP)
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if (qinst->src[i].file == QFILE_TEMP)
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reg_uses_remaining[qinst->src[i].index]++;
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reg_uses_remaining[qinst->src[i].index]++;
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}
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}
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if (qinst->op == QOP_TLB_PASSTHROUGH_Z_WRITE ||
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if (qinst->op == QOP_FRAG_Z)
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qinst->op == QOP_FRAG_Z)
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reg_in_use[3 + 32 + QPU_R_FRAG_PAYLOAD_ZW] = true;
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reg_in_use[3 + 32 + QPU_R_FRAG_PAYLOAD_ZW] = true;
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}
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}
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@ -362,6 +361,12 @@ vc4_generate_code(struct vc4_compile *c)
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if (reg.mux != QPU_MUX_R4)
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if (reg.mux != QPU_MUX_R4)
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continue;
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continue;
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break;
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break;
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case QOP_FRAG_Z:
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if (reg.mux != QPU_MUX_B ||
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reg.addr != QPU_R_FRAG_PAYLOAD_ZW) {
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continue;
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}
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break;
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default:
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default:
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if (reg.mux == QPU_MUX_R4)
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if (reg.mux == QPU_MUX_R4)
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continue;
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continue;
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@ -492,8 +497,9 @@ vc4_generate_code(struct vc4_compile *c)
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break;
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break;
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case QOP_FRAG_Z:
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case QOP_FRAG_Z:
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queue(c, qpu_a_ITOF(dst,
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/* QOP_FRAG_Z doesn't emit instructions, just
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qpu_rb(QPU_R_FRAG_PAYLOAD_ZW)));
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* allocates the register to the Z payload.
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*/
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break;
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break;
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case QOP_FRAG_RCP_W:
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case QOP_FRAG_RCP_W:
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@ -509,9 +515,8 @@ vc4_generate_code(struct vc4_compile *c)
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*last_inst(c) |= QPU_SF;
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*last_inst(c) |= QPU_SF;
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break;
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break;
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case QOP_TLB_PASSTHROUGH_Z_WRITE:
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case QOP_TLB_Z_WRITE:
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queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_Z),
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queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_Z), src[0]));
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qpu_rb(QPU_R_FRAG_PAYLOAD_ZW)));
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if (discard) {
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if (discard) {
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set_last_cond_add(c, QPU_COND_ZS);
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set_last_cond_add(c, QPU_COND_ZS);
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}
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}
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