radeonsi: add per-level dcc_enabled flags
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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60e93ddd06
commit
aa7fe70443
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@ -72,10 +72,10 @@ bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
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* dst: If overwriting the whole texture, discard DCC and use SDMA.
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* Otherwise, use the 3D path.
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*/
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if (rsrc->dcc_offset)
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if (rsrc->dcc_offset && rsrc->surface.level[src_level].dcc_enabled)
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return false;
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if (rdst->dcc_offset) {
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if (rdst->dcc_offset && rdst->surface.level[dst_level].dcc_enabled) {
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/* We can't discard DCC if the texture has been exported.
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* We can only discard DCC for the entire texture.
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*/
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@ -1872,7 +1872,7 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
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continue;
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}
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if (tex->dcc_offset) {
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if (tex->dcc_offset && tex->surface.level[0].dcc_enabled) {
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uint32_t reset_value;
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bool clear_words_needed;
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@ -360,6 +360,7 @@ struct radeon_surf_level {
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uint32_t pitch_bytes;
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uint32_t mode;
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uint64_t dcc_offset;
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bool dcc_enabled;
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};
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struct radeon_surf {
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@ -321,6 +321,13 @@ static void si_blit_decompress_color(struct pipe_context *ctx,
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if (rtex->dcc_offset && need_dcc_decompress) {
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custom_blend = sctx->custom_blend_dcc_decompress;
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/* disable levels without DCC */
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for (int i = first_level; i <= last_level; i++) {
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if (!rtex->dcc_offset ||
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!rtex->surface.level[i].dcc_enabled)
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level_mask &= ~(1 << i);
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}
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} else if (rtex->fmask.size) {
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custom_blend = sctx->custom_blend_decompress;
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} else {
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@ -331,7 +331,7 @@ void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
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is_stencil));
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state[4] |= S_008F20_PITCH(pitch - 1);
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if (tex->dcc_offset) {
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if (tex->dcc_offset && base_level_info->dcc_enabled) {
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state[6] |= S_008F28_COMPRESSION_EN(1);
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state[7] = (tex->resource.gpu_address +
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tex->dcc_offset +
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@ -591,14 +591,16 @@ static void si_set_shader_image(struct si_context *ctx,
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} else {
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static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
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struct r600_texture *tex = (struct r600_texture *)res;
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unsigned level;
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unsigned level = view->u.tex.level;
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unsigned width, height, depth;
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uint32_t *desc = descs->list + slot * 8;
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bool uses_dcc = tex->dcc_offset &&
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tex->surface.level[level].dcc_enabled;
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assert(!tex->is_depth);
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assert(tex->fmask.size == 0);
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if (tex->dcc_offset &&
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if (uses_dcc &&
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view->access & PIPE_IMAGE_ACCESS_WRITE) {
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/* If DCC can't be disabled, at least decompress it.
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* The decompression is relatively cheap if the surface
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@ -624,7 +626,6 @@ static void si_set_shader_image(struct si_context *ctx,
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* selecting a single slice for non-layered bindings
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* fails. It doesn't hurt the other targets.
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*/
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level = view->u.tex.level;
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width = u_minify(res->b.b.width0, level);
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height = u_minify(res->b.b.height0, level);
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depth = u_minify(res->b.b.depth0, level);
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@ -2443,7 +2443,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
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}
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cb_color_info = cb->cb_color_info | tex->cb_color_info;
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if (tex->dcc_offset)
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if (tex->dcc_offset && cb->level_info->dcc_enabled)
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cb_color_info |= S_028C70_DCC_ENABLE(1);
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radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
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@ -226,6 +226,10 @@ static int compute_level(struct amdgpu_winsys *ws,
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surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
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/* Clear DCC fields at the beginning. */
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surf_level->dcc_offset = 0;
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surf_level->dcc_enabled = false;
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if (AddrSurfInfoIn->flags.dccCompatible) {
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AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
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AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
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@ -239,15 +243,14 @@ static int compute_level(struct amdgpu_winsys *ws,
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if (ret == ADDR_OK) {
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surf_level->dcc_offset = surf->dcc_size;
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surf_level->dcc_enabled = true;
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surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
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surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
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} else {
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surf->dcc_size = 0;
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surf_level->dcc_offset = 0;
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}
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} else {
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surf->dcc_size = 0;
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surf_level->dcc_offset = 0;
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}
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return 0;
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@ -344,7 +347,8 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
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AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
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!(surf->flags & RADEON_SURF_SCANOUT) &&
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!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
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!compressed && AddrDccIn.numSamples <= 1;
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!compressed && AddrDccIn.numSamples <= 1 &&
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surf->last_level == 0;
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AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
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AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
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