radeonsi: convert constant buffers to si_descriptors
There is a new "class" si_buffer_resources, which should be good enough for implementing any kind of buffer bindings (constant buffers, vertex buffers, streamout buffers, shader storage buffers, etc.) I don't even keep a copy of pipe_constant_buffer - we don't need it. The main motivation behind this is to have a well-tested infrastrusture for setting up streamout buffers. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Tested-by: Tom Stellard <thomas.stellard@amd.com>
This commit is contained in:
Marek Olšák
parent
a81c3e00fe
commit
aa5c40f97c
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@ -115,13 +115,6 @@ struct r600_fence_block {
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struct list_head head;
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};
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struct r600_constbuf_state
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{
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struct pipe_constant_buffer cb[2];
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uint32_t enabled_mask;
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uint32_t dirty_mask;
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};
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#define SI_NUM_ATOMS(rctx) (sizeof((rctx)->atoms)/sizeof((rctx)->atoms.array[0]))
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#define SI_NUM_SHADERS (PIPE_SHADER_FRAGMENT+1)
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@ -138,6 +131,7 @@ struct r600_context {
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union {
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struct {
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struct r600_atom *const_buffers[SI_NUM_SHADERS];
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struct r600_atom *sampler_views[SI_NUM_SHADERS];
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};
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struct r600_atom *array[0];
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@ -164,7 +158,7 @@ struct r600_context {
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/* shader information */
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unsigned sprite_coord_enable;
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unsigned export_16bpc;
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struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
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struct si_buffer_resources const_buffers[SI_NUM_SHADERS];
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struct r600_textures_info samplers[SI_NUM_SHADERS];
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struct r600_resource *border_color_table;
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unsigned border_color_offset;
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@ -32,7 +32,7 @@
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#define SI_NUM_CONTEXTS 256
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static const uint32_t null_desc[8]; /* zeros */
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static uint32_t null_desc[8]; /* zeros */
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/* Set this if you want the 3D engine to wait until CP DMA is done.
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* It should be set on the last CP DMA packet. */
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@ -170,7 +170,7 @@ static void si_emit_shader_pointer(struct r600_context *rctx,
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static void si_emit_descriptors(struct r600_context *rctx,
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struct si_descriptors *desc,
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const uint32_t **descriptors)
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uint32_t **descriptors)
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{
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struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
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uint64_t va_base;
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@ -325,6 +325,135 @@ void si_set_sampler_view(struct r600_context *rctx, unsigned shader,
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si_update_descriptors(&views->desc);
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}
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/* BUFFER RESOURCES */
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static void si_emit_buffer_resources(struct r600_context *rctx, struct r600_atom *atom)
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{
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struct si_buffer_resources *buffers = (struct si_buffer_resources*)atom;
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si_emit_descriptors(rctx, &buffers->desc, buffers->desc_data);
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}
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static void si_init_buffer_resources(struct r600_context *rctx,
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struct si_buffer_resources *buffers,
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unsigned num_buffers, unsigned shader,
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unsigned shader_userdata_index,
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enum radeon_bo_usage shader_usage)
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{
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int i;
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buffers->num_buffers = num_buffers;
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buffers->shader_usage = shader_usage;
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buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
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buffers->desc_storage = CALLOC(num_buffers, sizeof(uint32_t) * 4);
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/* si_emit_descriptors only accepts an array of arrays.
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* This adds such an array. */
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buffers->desc_data = CALLOC(num_buffers, sizeof(uint32_t*));
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for (i = 0; i < num_buffers; i++) {
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buffers->desc_data[i] = &buffers->desc_storage[i*4];
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}
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si_init_descriptors(rctx, &buffers->desc,
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si_get_shader_user_data_base(shader) +
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shader_userdata_index*4, 4, num_buffers,
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si_emit_buffer_resources);
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}
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static void si_release_buffer_resources(struct si_buffer_resources *buffers)
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{
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int i;
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for (i = 0; i < Elements(buffers->buffers); i++) {
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pipe_resource_reference(&buffers->buffers[i], NULL);
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}
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FREE(buffers->buffers);
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FREE(buffers->desc_storage);
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FREE(buffers->desc_data);
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si_release_descriptors(&buffers->desc);
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}
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static void si_buffer_resources_begin_new_cs(struct r600_context *rctx,
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struct si_buffer_resources *buffers)
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{
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unsigned mask = buffers->desc.enabled_mask;
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/* Add relocations to the CS. */
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while (mask) {
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int i = u_bit_scan(&mask);
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r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
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(struct r600_resource*)buffers->buffers[i],
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buffers->shader_usage);
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}
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r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
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buffers->desc.buffer, RADEON_USAGE_READWRITE);
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si_emit_shader_pointer(rctx, &buffers->desc);
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}
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/* CONSTANT BUFFERS */
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static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint slot,
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struct pipe_constant_buffer *input)
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{
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struct r600_context *rctx = (struct r600_context *)ctx;
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struct si_buffer_resources *buffers = &rctx->const_buffers[shader];
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if (shader >= SI_NUM_SHADERS)
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return;
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rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
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assert(slot < buffers->num_buffers);
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pipe_resource_reference(&buffers->buffers[slot], NULL);
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if (input && (input->buffer || input->user_buffer)) {
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struct pipe_resource *buffer = NULL;
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uint64_t va;
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/* Upload the user buffer if needed. */
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if (input->user_buffer) {
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unsigned buffer_offset;
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r600_upload_const_buffer(rctx,
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(struct r600_resource**)&buffer, input->user_buffer,
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input->buffer_size, &buffer_offset);
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va = r600_resource_va(ctx->screen, buffer) + buffer_offset;
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} else {
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pipe_resource_reference(&buffer, input->buffer);
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va = r600_resource_va(ctx->screen, buffer) + input->buffer_offset;
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}
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/* Set the descriptor. */
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uint32_t *desc = buffers->desc_data[slot];
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desc[0] = va;
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desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
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S_008F04_STRIDE(0);
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desc[2] = input->buffer_size;
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desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
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S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
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S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
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S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
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S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
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S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
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buffers->buffers[slot] = buffer;
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r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
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(struct r600_resource*)buffer, buffers->shader_usage);
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buffers->desc.enabled_mask |= 1 << slot;
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} else {
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/* Clear the descriptor. */
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memset(buffers->desc_data[slot], 0, sizeof(uint32_t) * 4);
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buffers->desc.enabled_mask &= ~(1 << slot);
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}
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buffers->desc.dirty_mask |= 1 << slot;
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si_update_descriptors(&buffers->desc);
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}
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/* INIT/DEINIT */
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void si_init_all_descriptors(struct r600_context *rctx)
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@ -332,10 +461,18 @@ void si_init_all_descriptors(struct r600_context *rctx)
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int i;
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for (i = 0; i < SI_NUM_SHADERS; i++) {
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si_init_buffer_resources(rctx, &rctx->const_buffers[i],
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NUM_CONST_BUFFERS, i, SI_SGPR_CONST,
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RADEON_USAGE_READ);
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si_init_sampler_views(rctx, &rctx->samplers[i].views, i);
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rctx->atoms.const_buffers[i] = &rctx->const_buffers[i].desc.atom;
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rctx->atoms.sampler_views[i] = &rctx->samplers[i].views.desc.atom;
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}
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/* Set pipe_context functions. */
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rctx->b.b.set_constant_buffer = si_set_constant_buffer;
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}
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void si_release_all_descriptors(struct r600_context *rctx)
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@ -343,6 +480,7 @@ void si_release_all_descriptors(struct r600_context *rctx)
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int i;
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for (i = 0; i < SI_NUM_SHADERS; i++) {
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si_release_buffer_resources(&rctx->const_buffers[i]);
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si_release_sampler_views(&rctx->samplers[i].views);
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}
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}
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@ -352,6 +490,7 @@ void si_all_descriptors_begin_new_cs(struct r600_context *rctx)
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int i;
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for (i = 0; i < SI_NUM_SHADERS; i++) {
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si_buffer_resources_begin_new_cs(rctx, &rctx->const_buffers[i]);
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si_sampler_views_begin_new_cs(rctx, &rctx->samplers[i].views);
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}
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}
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@ -3016,46 +3016,6 @@ static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
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free(state);
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}
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/*
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* Constants
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*/
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static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
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struct pipe_constant_buffer *input)
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{
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struct r600_context *rctx = (struct r600_context *)ctx;
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struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
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struct pipe_constant_buffer *cb;
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const uint8_t *ptr;
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/* Note that the state tracker can unbind constant buffers by
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* passing NULL here.
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*/
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if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
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state->enabled_mask &= ~(1 << index);
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state->dirty_mask &= ~(1 << index);
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pipe_resource_reference(&state->cb[index].buffer, NULL);
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return;
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}
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cb = &state->cb[index];
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cb->buffer_size = input->buffer_size;
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ptr = input->user_buffer;
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if (ptr) {
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r600_upload_const_buffer(rctx,
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(struct r600_resource**)&cb->buffer, ptr,
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cb->buffer_size, &cb->buffer_offset);
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} else {
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/* Setup the hw buffer. */
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cb->buffer_offset = input->buffer_offset;
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pipe_resource_reference(&cb->buffer, input->buffer);
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}
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state->enabled_mask |= 1 << index;
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state->dirty_mask |= 1 << index;
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}
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/*
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* Vertex elements & buffers
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*/
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@ -3241,8 +3201,6 @@ void si_init_state_functions(struct r600_context *rctx)
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rctx->b.b.set_sample_mask = si_set_sample_mask;
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rctx->b.b.set_constant_buffer = si_set_constant_buffer;
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rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
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rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
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rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
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@ -92,11 +92,9 @@ union si_state {
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struct si_pm4_state *vs;
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struct si_pm4_state *vs_sampler_views;
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struct si_pm4_state *vs_sampler;
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struct si_pm4_state *vs_const;
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struct si_pm4_state *ps;
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struct si_pm4_state *ps_sampler_views;
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struct si_pm4_state *ps_sampler;
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struct si_pm4_state *ps_const;
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struct si_pm4_state *spi;
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struct si_pm4_state *vertex_buffers;
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struct si_pm4_state *texture_barrier;
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@ -114,6 +112,8 @@ union si_state {
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#define FMASK_TEX_OFFSET NUM_TEX_UNITS
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#define NUM_SAMPLER_VIEWS (FMASK_TEX_OFFSET+NUM_TEX_UNITS)
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#define NUM_CONST_BUFFERS 2
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/* This represents resource descriptors in memory, such as buffer resources,
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* image resources, and sampler states.
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*/
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@ -149,7 +149,16 @@ struct si_descriptors {
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struct si_sampler_views {
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struct si_descriptors desc;
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struct pipe_sampler_view *views[NUM_SAMPLER_VIEWS];
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const uint32_t *desc_data[NUM_SAMPLER_VIEWS];
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uint32_t *desc_data[NUM_SAMPLER_VIEWS];
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};
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struct si_buffer_resources {
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struct si_descriptors desc;
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unsigned num_buffers;
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enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
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struct pipe_resource **buffers; /* this has num_buffers elements */
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uint32_t *desc_storage; /* this has num_buffers*4 elements */
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uint32_t **desc_data; /* an array of pointers pointing to desc_storage */
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};
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#define si_pm4_block_idx(member) \
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@ -453,78 +453,6 @@ static void si_update_derived_state(struct r600_context *rctx)
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}
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}
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static void si_constant_buffer_update(struct r600_context *rctx)
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{
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struct pipe_context *ctx = &rctx->b.b;
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struct si_pm4_state *pm4;
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unsigned shader, i;
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uint64_t va;
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if (!rctx->constbuf_state[PIPE_SHADER_VERTEX].dirty_mask &&
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!rctx->constbuf_state[PIPE_SHADER_FRAGMENT].dirty_mask)
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return;
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for (shader = PIPE_SHADER_VERTEX ; shader <= PIPE_SHADER_FRAGMENT; shader++) {
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struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
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pm4 = CALLOC_STRUCT(si_pm4_state);
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if (!pm4)
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continue;
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si_pm4_inval_shader_cache(pm4);
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si_pm4_sh_data_begin(pm4);
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for (i = 0; i < 2; i++) {
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if (state->enabled_mask & (1 << i)) {
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struct pipe_constant_buffer *cb = &state->cb[i];
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struct r600_resource *rbuffer = r600_resource(cb->buffer);
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va = r600_resource_va(ctx->screen, (void*)rbuffer);
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va += cb->buffer_offset;
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si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
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/* Fill in a T# buffer resource description */
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si_pm4_sh_data_add(pm4, va);
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si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
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S_008F04_STRIDE(0)));
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si_pm4_sh_data_add(pm4, cb->buffer_size);
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si_pm4_sh_data_add(pm4, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
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S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
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S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
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S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
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S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
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S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32));
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} else {
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/* Fill in an empty T# buffer resource description */
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si_pm4_sh_data_add(pm4, 0);
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si_pm4_sh_data_add(pm4, 0);
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si_pm4_sh_data_add(pm4, 0);
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si_pm4_sh_data_add(pm4, 0);
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}
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}
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switch (shader) {
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case PIPE_SHADER_VERTEX:
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si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_CONST);
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si_pm4_set_state(rctx, vs_const, pm4);
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break;
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case PIPE_SHADER_FRAGMENT:
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si_pm4_sh_data_end(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, SI_SGPR_CONST);
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si_pm4_set_state(rctx, ps_const, pm4);
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break;
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default:
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R600_ERR("unsupported %d\n", shader);
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FREE(pm4);
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return;
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}
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state->dirty_mask = 0;
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}
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}
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static void si_vertex_buffer_update(struct r600_context *rctx)
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{
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struct pipe_context *ctx = &rctx->b.b;
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@ -653,7 +581,6 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
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return;
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si_update_derived_state(rctx);
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si_constant_buffer_update(rctx);
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si_vertex_buffer_update(rctx);
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if (info->indexed) {
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@ -678,7 +605,14 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
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si_state_draw(rctx, info, &ib);
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/* Cache flushing via CP_COHER_CNTL. */
|
||||
cp_coher_cntl = si_pm4_sync_flags(rctx);
|
||||
|
||||
if (rctx->b.flags & R600_CONTEXT_INV_CONST_CACHE) {
|
||||
cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
|
||||
S_0085F0_SH_KCACHE_ACTION_ENA(1);
|
||||
}
|
||||
|
||||
if (cp_coher_cntl) {
|
||||
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue