r600/shader: add support for load/store/atomic ops on images.
This adds support to the shader assembler for load/store/atomic ops on images which are handled via the RAT operations. Tested-By: Gert Wollny <gw.fossdev@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
parent
a6b3792843
commit
aa38bf658f
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@ -969,6 +969,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
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case TGSI_FILE_SAMPLER:
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case TGSI_FILE_SAMPLER_VIEW:
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case TGSI_FILE_ADDRESS:
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case TGSI_FILE_IMAGE:
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break;
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case TGSI_FILE_HW_ATOMIC:
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@ -3074,6 +3075,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
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case PIPE_SHADER_FRAGMENT:
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shader->two_side = key.ps.color_two_side;
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shader->atomic_base = key.ps.first_atomic_counter;
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shader->rat_base = key.ps.nr_cbufs;
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break;
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default:
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break;
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@ -7775,14 +7777,321 @@ static int tgsi_load_gds(struct r600_shader_ctx *ctx)
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return 0;
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}
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/* this fixes up 1D arrays properly */
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static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int *idx_gpr)
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{
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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int r, i;
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struct r600_bytecode_alu alu;
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int temp_reg = r600_get_temp(ctx);
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for (i = 0; i < 4; i++) {
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bool def_val = true, write_zero = false;
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_MOV;
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alu.dst.sel = temp_reg;
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alu.dst.chan = i;
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switch (inst->Memory.Texture) {
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case TGSI_TEXTURE_BUFFER:
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case TGSI_TEXTURE_1D:
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if (i == 1 || i == 2 || i == 3) {
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write_zero = true;
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}
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break;
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case TGSI_TEXTURE_1D_ARRAY:
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if (i == 1 || i == 3)
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write_zero = true;
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else if (i == 2) {
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r600_bytecode_src(&alu.src[0], &ctx->src[src_index], 1);
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def_val = false;
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}
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break;
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case TGSI_TEXTURE_2D:
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if (i == 2 || i == 3)
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write_zero = true;
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break;
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default:
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if (i == 3)
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write_zero = true;
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break;
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}
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if (write_zero) {
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alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
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alu.src[0].value = 0;
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} else if (def_val) {
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r600_bytecode_src(&alu.src[0], &ctx->src[src_index], i);
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}
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if (i == 3)
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alu.last = 1;
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alu.dst.write = 1;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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}
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*idx_gpr = temp_reg;
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return 0;
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}
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static int tgsi_load_rat(struct r600_shader_ctx *ctx)
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{
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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/* have to work out the offset into the RAT immediate return buffer */
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struct r600_bytecode_vtx vtx;
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struct r600_bytecode_cf *cf;
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int r;
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int idx_gpr;
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unsigned format, num_format, format_comp, endian;
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const struct util_format_description *desc;
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unsigned rat_index_mode;
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unsigned immed_base;
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rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
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immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
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r = load_index_src(ctx, 1, &idx_gpr);
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if (r)
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return r;
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if (rat_index_mode)
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egcm_load_index_reg(ctx->bc, 1, false);
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r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
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cf = ctx->bc->cf_last;
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cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
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cf->rat.inst = V_RAT_INST_NOP_RTN;
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cf->rat.index_mode = rat_index_mode;
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cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
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cf->output.gpr = ctx->thread_id_gpr;
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cf->output.index_gpr = idx_gpr;
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cf->output.comp_mask = 0xf;
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cf->output.burst_count = 1;
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cf->vpm = 1;
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cf->barrier = 1;
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cf->mark = 1;
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cf->output.elem_size = 0;
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r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
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cf = ctx->bc->cf_last;
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cf->barrier = 1;
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desc = util_format_description(inst->Memory.Format);
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r600_vertex_data_type(inst->Memory.Format,
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&format, &num_format, &format_comp, &endian);
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memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
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vtx.op = FETCH_OP_VFETCH;
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vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
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vtx.buffer_index_mode = rat_index_mode;
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vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
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vtx.src_gpr = ctx->thread_id_gpr;
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vtx.src_sel_x = 1;
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vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
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vtx.dst_sel_x = desc->swizzle[0];
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vtx.dst_sel_y = desc->swizzle[1];
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vtx.dst_sel_z = desc->swizzle[2];
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vtx.dst_sel_w = desc->swizzle[3];
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vtx.srf_mode_all = 1;
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vtx.data_format = format;
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vtx.num_format_all = num_format;
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vtx.format_comp_all = format_comp;
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vtx.endian = endian;
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vtx.offset = 0;
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vtx.mega_fetch_count = 3;
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r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
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if (r)
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return r;
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cf = ctx->bc->cf_last;
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cf->barrier = 1;
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return 0;
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}
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static int tgsi_load(struct r600_shader_ctx *ctx)
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{
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
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return tgsi_load_rat(ctx);
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if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
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return tgsi_load_gds(ctx);
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return 0;
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}
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static int tgsi_store_rat(struct r600_shader_ctx *ctx)
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{
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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struct r600_bytecode_cf *cf;
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bool src_requires_loading = false;
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int val_gpr, idx_gpr;
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int r, i;
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unsigned rat_index_mode;
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rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
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r = load_index_src(ctx, 0, &idx_gpr);
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if (r)
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return r;
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if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
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src_requires_loading = true;
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if (src_requires_loading) {
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struct r600_bytecode_alu alu;
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for (i = 0; i < 4; i++) {
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_MOV;
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alu.dst.sel = ctx->temp_reg;
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alu.dst.chan = i;
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r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
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if (i == 3)
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alu.last = 1;
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alu.dst.write = 1;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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}
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val_gpr = ctx->temp_reg;
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} else
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val_gpr = tgsi_tex_get_src_gpr(ctx, 1);
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if (rat_index_mode)
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egcm_load_index_reg(ctx->bc, 1, false);
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r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
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cf = ctx->bc->cf_last;
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cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
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cf->rat.inst = V_RAT_INST_STORE_TYPED;
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cf->rat.index_mode = rat_index_mode;
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cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
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cf->output.gpr = val_gpr;
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cf->output.index_gpr = idx_gpr;
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cf->output.comp_mask = 0xf;
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cf->output.burst_count = 1;
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cf->vpm = 1;
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cf->barrier = 1;
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cf->output.elem_size = 0;
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return 0;
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}
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static int tgsi_store(struct r600_shader_ctx *ctx)
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{
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return tgsi_store_rat(ctx);
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}
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static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx)
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{
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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/* have to work out the offset into the RAT immediate return buffer */
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struct r600_bytecode_alu alu;
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struct r600_bytecode_vtx vtx;
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struct r600_bytecode_cf *cf;
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int r;
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int idx_gpr;
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unsigned format, num_format, format_comp, endian;
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const struct util_format_description *desc;
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unsigned rat_index_mode;
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unsigned immed_base;
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immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
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assert (inst->Src[0].Register.File == TGSI_FILE_IMAGE);
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rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
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r = load_index_src(ctx, 1, &idx_gpr);
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if (r)
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return r;
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if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_MOV;
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alu.dst.sel = ctx->thread_id_gpr;
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alu.dst.chan = 0;
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alu.dst.write = 1;
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r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
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alu.last = 1;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_MOV;
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alu.dst.sel = ctx->thread_id_gpr;
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alu.dst.chan = 3;
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alu.dst.write = 1;
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r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
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alu.last = 1;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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} else {
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_MOV;
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alu.dst.sel = ctx->thread_id_gpr;
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alu.dst.chan = 0;
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alu.dst.write = 1;
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r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
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alu.last = 1;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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}
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if (rat_index_mode)
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egcm_load_index_reg(ctx->bc, 1, false);
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r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
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cf = ctx->bc->cf_last;
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cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
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cf->rat.inst = ctx->inst_info->op;
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cf->rat.index_mode = rat_index_mode;
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cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
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cf->output.gpr = ctx->thread_id_gpr;
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cf->output.index_gpr = idx_gpr;
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cf->output.comp_mask = 0xf;
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cf->output.burst_count = 1;
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cf->vpm = 1;
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cf->barrier = 1;
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cf->mark = 1;
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cf->output.elem_size = 0;
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r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
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cf = ctx->bc->cf_last;
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cf->barrier = 1;
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cf->cf_addr = 1;
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desc = util_format_description(inst->Memory.Format);
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r600_vertex_data_type(inst->Memory.Format,
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&format, &num_format, &format_comp, &endian);
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memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
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vtx.op = FETCH_OP_VFETCH;
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vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
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vtx.buffer_index_mode = rat_index_mode;
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vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
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vtx.src_gpr = ctx->thread_id_gpr;
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vtx.src_sel_x = 1;
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vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
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vtx.dst_sel_x = desc->swizzle[0];
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vtx.dst_sel_y = 7;
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vtx.dst_sel_z = 7;
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vtx.dst_sel_w = 7;
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vtx.use_const_fields = 0;
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vtx.srf_mode_all = 1;
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vtx.data_format = format;
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vtx.num_format_all = num_format;
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vtx.format_comp_all = format_comp;
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vtx.endian = endian;
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vtx.offset = 0;
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vtx.mega_fetch_count = 0xf;
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r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
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if (r)
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return r;
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cf = ctx->bc->cf_last;
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cf->vpm = 1;
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cf->barrier = 1;
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return 0;
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}
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static int get_gds_op(int opcode)
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{
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switch (opcode) {
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@ -7881,6 +8190,8 @@ static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
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static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
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{
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
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return tgsi_atomic_op_rat(ctx);
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if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
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return tgsi_atomic_op_gds(ctx);
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return 0;
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@ -9540,7 +9851,7 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
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[TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
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[TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
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[TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
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[TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
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[113] = { ALU_OP0_NOP, tgsi_unsupported},
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[114] = { ALU_OP0_NOP, tgsi_unsupported},
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[115] = { ALU_OP0_NOP, tgsi_unsupported},
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@ -9590,7 +9901,7 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
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[TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
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[TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
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[TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
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[TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
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[163] = { ALU_OP0_NOP, tgsi_unsupported},
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[164] = { ALU_OP0_NOP, tgsi_unsupported},
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[165] = { ALU_OP0_NOP, tgsi_unsupported},
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@ -9763,7 +10074,7 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
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[TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
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[TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
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[TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
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[TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
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[TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
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[113] = { ALU_OP0_NOP, tgsi_unsupported},
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[114] = { ALU_OP0_NOP, tgsi_unsupported},
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[115] = { ALU_OP0_NOP, tgsi_unsupported},
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@ -9813,7 +10124,7 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
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[TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
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[TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
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[TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
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[TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
|
||||
[TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
|
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[163] = { ALU_OP0_NOP, tgsi_unsupported},
|
||||
[164] = { ALU_OP0_NOP, tgsi_unsupported},
|
||||
[165] = { ALU_OP0_NOP, tgsi_unsupported},
|
||||
|
|
|
|||
Loading…
Reference in New Issue