Adds support for MGA DRM version 3.2.
This patch makes use of two of the new ioctls added in MGA DRM version 3.2. Specifically, the DRM_MGA_SET_FENCE and DRM_MGA_WAIT_FENCE ioctls are used in mgaWaitForFrameCompletion. As a result the MMIO register region and the primary DMA region are *not* mapped (if DRM 3.2 is available). This patch does *not* make use of the new get_param query was added to differentiate between G4x0 cards and G550 cards. That is left to a future update. Xorg bug: 3259 Reviewed by: Eric Anholt
This commit is contained in:
Ian Romanick
parent
fb818a0b11
commit
aa26915472
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@ -31,6 +31,7 @@
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include "drm.h"
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#include "mga_drm.h"
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#include "mga_xmesa.h"
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@ -264,22 +265,30 @@ mgaInitDriver(__DRIscreenPrivate *sPriv)
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* primary DMA region base address needs to be known is so that the driver
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* can busy wait for certain DMA operations to complete (see
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* mgaWaitForFrameCompletion in mgaioctl.c).
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*
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* Starting with MGA DRM version 3.2, these are completely unneeded as
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* there is a new, in-kernel mechanism for handling the wait.
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*/
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mgaScreen->mmio.handle = serverInfo->registers.handle;
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mgaScreen->mmio.size = serverInfo->registers.size;
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if ( drmMap( sPriv->fd,
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mgaScreen->mmio.handle, mgaScreen->mmio.size,
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&mgaScreen->mmio.map ) < 0 ) {
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FREE( mgaScreen );
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sPriv->private = NULL;
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__driUtilMessage( "Couldn't map MMIO registers" );
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return GL_FALSE;
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if (mgaScreen->sPriv->drmMinor < 2) {
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mgaScreen->mmio.handle = serverInfo->registers.handle;
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mgaScreen->mmio.size = serverInfo->registers.size;
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if ( drmMap( sPriv->fd,
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mgaScreen->mmio.handle, mgaScreen->mmio.size,
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&mgaScreen->mmio.map ) < 0 ) {
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FREE( mgaScreen );
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sPriv->private = NULL;
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__driUtilMessage( "Couldn't map MMIO registers" );
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return GL_FALSE;
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}
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mgaScreen->primary.handle = serverInfo->primary.handle;
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mgaScreen->primary.size = serverInfo->primary.size;
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}
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else {
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(void) memset( & mgaScreen->primary, 0, sizeof( mgaScreen->primary ) );
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(void) memset( & mgaScreen->mmio, 0, sizeof( mgaScreen->mmio ) );
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}
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mgaScreen->primary.handle = serverInfo->primary.handle;
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mgaScreen->primary.size = serverInfo->primary.size;
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mgaScreen->textureOffset[MGA_CARD_HEAP] = serverInfo->textureOffset;
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mgaScreen->textureOffset[MGA_AGP_HEAP] = (serverInfo->agpTextureOffset |
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@ -29,6 +29,7 @@
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#ifndef MGALIB_INC
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#define MGALIB_INC
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#include <stdint.h>
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#include "drm.h"
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#include "mga_drm.h"
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#include "dri_util.h"
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@ -268,6 +269,8 @@ struct mga_context_t {
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GLuint swap_count;
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GLuint swap_missed_count;
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uint32_t last_frame_fence;
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PFNGLXGETUSTPROC get_ust;
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/* Drawable, cliprect and scissor information
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@ -41,7 +41,7 @@
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#include "mga_xmesa.h"
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#include "utils.h"
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#define DRIVER_DATE "20030328"
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#define DRIVER_DATE "20050609"
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/***************************************
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@ -50,6 +50,49 @@
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#include "vblank.h"
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int
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mgaSetFence( mgaContextPtr mmesa, uint32_t * fence )
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{
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int ret = ENOSYS;
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if ( mmesa->driScreen->drmMinor >= 2 ) {
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ret = drmCommandWriteRead( mmesa->driScreen->fd, DRM_MGA_SET_FENCE,
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fence, sizeof( uint32_t ));
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if (ret) {
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fprintf(stderr, "drmMgaSetFence: %d\n", ret);
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exit(1);
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}
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}
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return ret;
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}
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int
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mgaWaitFence( mgaContextPtr mmesa, uint32_t fence, uint32_t * curr_fence )
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{
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int ret = ENOSYS;
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if ( mmesa->driScreen->drmMinor >= 2 ) {
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uint32_t temp = fence;
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ret = drmCommandWriteRead( mmesa->driScreen->fd,
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DRM_MGA_WAIT_FENCE,
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& temp, sizeof( uint32_t ));
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if (ret) {
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fprintf(stderr, "drmMgaSetFence: %d\n", ret);
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exit(1);
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}
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if ( curr_fence ) {
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*curr_fence = temp;
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}
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}
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return ret;
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}
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static void mga_iload_dma_ioctl(mgaContextPtr mmesa,
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unsigned long dest,
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int length)
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@ -294,58 +337,64 @@ mgaClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
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* \bug
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* The loop in this function should have some sort of a timeout mechanism.
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*
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* \todo
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* This routine should be modified to wait on a semaphore. To do this,
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* the DRM would have to queue an interrupt when the swap command was
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* put in the DMA buffer. When the interrupt occured, the DRM would UP
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* the semaphore. This function would then just DOWN the semaphore.
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* \warning
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* This routine used to assume that the hardware lock was held on entry. It
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* now assumes that the lock is \b not held on entry.
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*/
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static void mgaWaitForFrameCompletion( mgaContextPtr mmesa )
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{
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unsigned wait = 0;
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const GLuint last_frame = mmesa->sarea->last_frame.head;
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const GLuint last_wrap = mmesa->sarea->last_frame.wrap;
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if ( mgaWaitFence( mmesa, mmesa->last_frame_fence, NULL ) == ENOSYS ) {
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unsigned wait = 0;
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GLuint last_frame;
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GLuint last_wrap;
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/* The DMA routines in the kernel track a couple values in the SAREA that
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* we use here. The number of times that the primary DMA buffer has
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* "wrapped" around is tracked in last_wrap. In addition, the wrap count
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* and the buffer position at the end of the last frame are stored in
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* last_frame.wrap and last_frame.head.
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*
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* By comparing the wrap counts and the current DMA pointer value (read
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* directly from the hardware) to last_frame.head, we can determine when
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* the graphics processor has processed all of the commands for the last
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* frame.
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*
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* In this case "last frame" means the frame of the *previous* swap-
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* buffers call. This is done to prevent queuing a second buffer swap
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* before the previous swap is executed.
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*/
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while ( 1 ) {
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if ( last_wrap < mmesa->sarea->last_wrap ||
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( last_wrap == mmesa->sarea->last_wrap &&
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last_frame <= (MGA_READ( MGAREG_PRIMADDRESS ) -
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mmesa->primary_offset) ) ) {
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break;
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}
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if ( 0 ) {
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wait++;
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fprintf( stderr, " last: head=0x%06x wrap=%d\n",
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last_frame, last_wrap );
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fprintf( stderr, " head: head=0x%06lx wrap=%d\n",
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(long)(MGA_READ( MGAREG_PRIMADDRESS ) - mmesa->primary_offset),
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mmesa->sarea->last_wrap );
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}
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UPDATE_LOCK( mmesa, DRM_LOCK_FLUSH );
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LOCK_HARDWARE( mmesa );
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last_frame = mmesa->sarea->last_frame.head;
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last_wrap = mmesa->sarea->last_frame.wrap;
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UNLOCK_HARDWARE( mmesa );
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DO_USLEEP( 1 );
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LOCK_HARDWARE( mmesa );
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}
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if ( wait )
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fprintf( stderr, "\n" );
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/* The DMA routines in the kernel track a couple values in the SAREA
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* that we use here. The number of times that the primary DMA buffer
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* has "wrapped" around is tracked in last_wrap. In addition, the
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* wrap count and the buffer position at the end of the last frame are
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* stored in last_frame.wrap and last_frame.head.
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*
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* By comparing the wrap counts and the current DMA pointer value
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* (read directly from the hardware) to last_frame.head, we can
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* determine when the graphics processor has processed all of the
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* commands for the last frame.
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*
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* In this case "last frame" means the frame of the *previous* swap-
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* buffers call. This is done to prevent queuing a second buffer swap
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* before the previous swap is executed.
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*/
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while ( 1 ) {
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if ( last_wrap < mmesa->sarea->last_wrap ||
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( last_wrap == mmesa->sarea->last_wrap &&
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last_frame <= (MGA_READ( MGAREG_PRIMADDRESS ) -
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mmesa->primary_offset) ) ) {
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break;
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}
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if ( 0 ) {
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wait++;
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fprintf( stderr, " last: head=0x%06x wrap=%d\n",
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last_frame, last_wrap );
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fprintf( stderr, " head: head=0x%06lx wrap=%d\n",
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(long)(MGA_READ( MGAREG_PRIMADDRESS ) - mmesa->primary_offset),
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mmesa->sarea->last_wrap );
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}
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UPDATE_LOCK( mmesa, DRM_LOCK_FLUSH );
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UNLOCK_HARDWARE( mmesa );
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DO_USLEEP( 1 );
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LOCK_HARDWARE( mmesa );
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}
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if ( wait )
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fprintf( stderr, "\n" );
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UNLOCK_HARDWARE( mmesa );
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}
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}
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@ -370,9 +419,7 @@ void mgaCopyBuffer( const __DRIdrawablePrivate *dPriv )
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FLUSH_BATCH( mmesa );
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LOCK_HARDWARE( mmesa );
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mgaWaitForFrameCompletion( mmesa );
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UNLOCK_HARDWARE( mmesa );
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driWaitForVBlank( dPriv, & mmesa->vbl_seq, mmesa->vblank_flags,
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& missed_target );
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if ( missed_target ) {
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@ -410,6 +457,7 @@ void mgaCopyBuffer( const __DRIdrawablePrivate *dPriv )
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}
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}
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(void) mgaSetFence( mmesa, & mmesa->last_frame_fence );
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UNLOCK_HARDWARE( mmesa );
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mmesa->dirty |= MGA_UPLOAD_CLIPRECTS;
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@ -425,17 +473,12 @@ void mgaCopyBuffer( const __DRIdrawablePrivate *dPriv )
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*
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* \param ctx Context where the \c glFinish command was issued.
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*
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* \todo
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* This is overkill. The lock, update-lock, unlock sequence grabs the
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* hardware, waits for \b all hardware activity to finish, then releases the
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* hardware. A better way would be to flush the pending DMA buffers, emit
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* a SOFTRAP, and wait for the SOFTRAP.
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*
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* \sa glFinish, mgaFlush, mgaFlushDMA
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*/
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static void mgaFinish( GLcontext *ctx )
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{
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mgaContextPtr mmesa = MGA_CONTEXT(ctx);
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uint32_t fence;
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LOCK_HARDWARE( mmesa );
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@ -443,12 +486,18 @@ static void mgaFinish( GLcontext *ctx )
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mgaFlushVerticesLocked( mmesa );
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}
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if (MGA_DEBUG&DEBUG_VERBOSE_IOCTL) {
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fprintf(stderr, "mgaRegetLockQuiescent\n");
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if ( mgaSetFence( mmesa, & fence ) == 0 ) {
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UNLOCK_HARDWARE( mmesa );
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(void) mgaWaitFence( mmesa, fence, NULL );
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}
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else {
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if (MGA_DEBUG&DEBUG_VERBOSE_IOCTL) {
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fprintf(stderr, "mgaRegetLockQuiescent\n");
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}
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UPDATE_LOCK( mmesa, DRM_LOCK_QUIESCENT | DRM_LOCK_FLUSH );
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UNLOCK_HARDWARE( mmesa );
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UPDATE_LOCK( mmesa, DRM_LOCK_QUIESCENT | DRM_LOCK_FLUSH );
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UNLOCK_HARDWARE( mmesa );
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}
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}
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