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intel: Switch the order of the 2x MSAA sample positions 

The Vulkan 1.1.82 spec flipped the order to better match D3D.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
This commit is contained in:
Jason Ekstrand 2018-07-23 08:02:46 -07:00
parent 8a87138885
commit a9f7bcfdf9
4 changed files with 24 additions and 14 deletions
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12
src/intel/blorp/blorp_blit.c
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@ -776,6 +776,14 @@ blorp_nir_manual_blend_bilinear(nir_builder *b, nir_ssa_def *pos,
* grid of samples with in a pixel. Sample number layout shows the
* rectangular grid of samples roughly corresponding to the real sample
* locations with in a pixel.
*
* In the case of 2x MSAA, the layout of sample indices is reversed from
* the layout of sample numbers:
*
* sample index layout : --------- sample number layout : ---------
* | 0 | 1 | | 1 | 0 |
* --------- ---------
*
* In case of 4x MSAA, layout of sample indices matches the layout of
* sample numbers:
* ---------
@ -819,7 +827,9 @@ blorp_nir_manual_blend_bilinear(nir_builder *b, nir_ssa_def *pos,
key->x_scale * key->y_scale));
sample = nir_f2i32(b, sample);
if (tex_samples == 8) {
if (tex_samples == 2) {
sample = nir_isub(b, nir_imm_int(b, 1), sample);
} else if (tex_samples == 8) {
sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x64210573),
nir_ishl(b, sample, nir_imm_int(b, 2))),
nir_imm_int(b, 0xf));

8
src/intel/common/gen_sample_positions.h
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@ -42,10 +42,10 @@ prefix##0YOffset = 0.5;
* c 1
*/
#define GEN_SAMPLE_POS_2X(prefix) \
prefix##0XOffset = 0.25; \
prefix##0YOffset = 0.25; \
prefix##1XOffset = 0.75; \
prefix##1YOffset = 0.75;
prefix##0XOffset = 0.75; \
prefix##0YOffset = 0.75; \
prefix##1XOffset = 0.25; \
prefix##1YOffset = 0.25;
/**
* Sample positions:

8
src/mesa/drivers/dri/i965/brw_multisample_state.h
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@ -38,13 +38,13 @@
/**
* 1x MSAA has a single sample at the center: (0.5, 0.5) -> (0x8, 0x8).
*
* 2x MSAA sample positions are (0.25, 0.25) and (0.75, 0.75):
* 2x MSAA sample positions are (0.75, 0.75) and (0.25, 0.25):
* 4 c
* 4 0
* c 1
* 4 1
* c 0
*/
static const uint32_t
brw_multisample_positions_1x_2x = 0x0088cc44;
brw_multisample_positions_1x_2x = 0x008844cc;
/**
* Sample positions:

10
src/mesa/drivers/dri/i965/gen6_multisample_state.c
View File

@ -68,10 +68,10 @@ gen6_get_sample_position(struct gl_context *ctx,
* index layout in case of 2X and 4x MSAA, but they are different in
* case of 8X MSAA.
*
* 2X MSAA sample index / number layout
* ---------
* | 0 | 1 |
* ---------
* 8X MSAA sample index layout 8x MSAA sample number layout
* --------- ---------
* | 0 | 1 | | 1 | 0 |
* --------- ---------
*
* 4X MSAA sample index / number layout
* ---------
@ -107,7 +107,7 @@ gen6_get_sample_position(struct gl_context *ctx,
void
gen6_set_sample_maps(struct gl_context *ctx)
{
uint8_t map_2x[2] = {0, 1};
uint8_t map_2x[2] = {1, 0};
uint8_t map_4x[4] = {0, 1, 2, 3};
uint8_t map_8x[8] = {3, 7, 5, 0, 1, 2, 4, 6};
uint8_t map_16x[16] = { 15, 10, 9, 7, 4, 1, 3, 13,