i965/vec4: Add a helper function to emit VS_OPCODE_PULL_CONSTANT_LOAD
There were three places in the visitor that had a similar chunk of code to emit the VS_OPCODE_PULL_CONSTANT_LOAD opcode using a register for the offset. This patch combines the chunks into a helper function to reduce the code duplication. It will also be useful in the next patch to expand what happens on Gen9+. This shouldn't introduce any functional changes. Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
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@ -364,6 +364,11 @@ public:
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dst_reg dst,
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src_reg orig_src,
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int base_offset);
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void emit_pull_constant_load_reg(dst_reg dst,
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src_reg surf_index,
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src_reg offset,
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bblock_t *before_block,
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vec4_instruction *before_inst);
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src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
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vec4_instruction *inst, src_reg src);
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@ -1296,6 +1296,63 @@ vec4_visitor::emit_lrp(const dst_reg &dst,
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}
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}
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/**
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* Emits the instructions needed to perform a pull constant load. before_block
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* and before_inst can be NULL in which case the instruction will be appended
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* to the end of the instruction list.
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*/
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void
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vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
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src_reg surf_index,
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src_reg offset_reg,
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bblock_t *before_block,
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vec4_instruction *before_inst)
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{
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assert((before_inst == NULL && before_block == NULL) ||
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(before_inst && before_block));
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vec4_instruction *pull;
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if (brw->gen >= 7) {
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dst_reg grf_offset = dst_reg(this, glsl_type::int_type);
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/* We have to use a message header on Skylake to get SIMD4x2 mode.
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* Reserve space for the register.
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*/
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if (brw->gen >= 9) {
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grf_offset.reg_offset++;
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alloc.sizes[grf_offset.reg] = 2;
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}
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grf_offset.type = offset_reg.type;
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pull = MOV(grf_offset, offset_reg);
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if (before_inst)
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emit_before(before_block, before_inst, pull);
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else
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emit(pull);
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pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
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dst,
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surf_index,
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src_reg(grf_offset));
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pull->mlen = 1;
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} else {
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pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD,
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dst,
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surf_index,
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offset_reg);
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pull->base_mrf = 14;
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pull->mlen = 1;
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}
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if (before_inst)
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emit_before(before_block, before_inst, pull);
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else
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emit(pull);
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}
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void
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vec4_visitor::visit(ir_expression *ir)
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{
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@ -1774,36 +1831,10 @@ vec4_visitor::visit(ir_expression *ir)
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emit(SHR(dst_reg(offset), op[1], src_reg(4)));
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}
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if (brw->gen >= 7) {
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dst_reg grf_offset = dst_reg(this, glsl_type::int_type);
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/* We have to use a message header on Skylake to get SIMD4x2 mode.
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* Reserve space for the register.
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*/
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if (brw->gen >= 9) {
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grf_offset.reg_offset++;
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alloc.sizes[grf_offset.reg] = 2;
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}
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grf_offset.type = offset.type;
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emit(MOV(grf_offset, offset));
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vec4_instruction *pull =
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emit(new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
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dst_reg(packed_consts),
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surf_index,
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src_reg(grf_offset)));
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pull->mlen = 1;
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} else {
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vec4_instruction *pull =
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emit(new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD,
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dst_reg(packed_consts),
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surf_index,
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offset));
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pull->base_mrf = 14;
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pull->mlen = 1;
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}
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emit_pull_constant_load_reg(dst_reg(packed_consts),
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surf_index,
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offset,
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NULL, NULL /* before_block/inst */);
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packed_consts.swizzle = brw_swizzle_for_size(ir->type->vector_elements);
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packed_consts.swizzle += BRW_SWIZZLE4(const_offset % 16 / 4,
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@ -3475,32 +3506,11 @@ vec4_visitor::emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
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src_reg index = src_reg(prog_data->base.binding_table.pull_constants_start);
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src_reg offset = get_pull_constant_offset(block, inst, orig_src.reladdr,
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reg_offset);
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vec4_instruction *load;
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if (brw->gen >= 7) {
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dst_reg grf_offset = dst_reg(this, glsl_type::int_type);
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/* We have to use a message header on Skylake to get SIMD4x2 mode.
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* Reserve space for the register.
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*/
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if (brw->gen >= 9) {
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grf_offset.reg_offset++;
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alloc.sizes[grf_offset.reg] = 2;
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}
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grf_offset.type = offset.type;
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emit_before(block, inst, MOV(grf_offset, offset));
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load = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
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temp, index, src_reg(grf_offset));
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load->mlen = 1;
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} else {
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load = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD,
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temp, index, offset);
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load->base_mrf = 14;
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load->mlen = 1;
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}
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emit_before(block, inst, load);
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emit_pull_constant_load_reg(temp,
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index,
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offset,
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block, inst);
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}
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/**
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@ -528,14 +528,6 @@ vec4_vs_visitor::get_vp_src_reg(const prog_src_register &src)
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/* Add the small constant index to the address register */
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src_reg reladdr = src_reg(this, glsl_type::int_type);
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/* We have to use a message header on Skylake to get SIMD4x2 mode.
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* Reserve space for the register.
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*/
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if (brw->gen >= 9) {
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reladdr.reg_offset++;
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alloc.sizes[reladdr.reg] = 2;
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}
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dst_reg dst_reladdr = dst_reg(reladdr);
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dst_reladdr.writemask = WRITEMASK_X;
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emit(ADD(dst_reladdr, this->vp_addr_reg, src_reg(src.Index)));
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@ -553,20 +545,11 @@ vec4_vs_visitor::get_vp_src_reg(const prog_src_register &src)
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result = src_reg(this, glsl_type::vec4_type);
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src_reg surf_index = src_reg(unsigned(prog_data->base.binding_table.pull_constants_start));
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vec4_instruction *load;
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if (brw->gen >= 7) {
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load = new(mem_ctx)
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vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
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dst_reg(result), surf_index, reladdr);
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load->mlen = 1;
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} else {
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load = new(mem_ctx)
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vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD,
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dst_reg(result), surf_index, reladdr);
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load->base_mrf = 14;
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load->mlen = 1;
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}
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emit(load);
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emit_pull_constant_load_reg(dst_reg(result),
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surf_index,
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reladdr,
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NULL, NULL /* before_block/inst */);
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break;
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}
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