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iris: Demote DC flush to HDC flush in cache tracker 

FLUSH_HDC is sufficient to flush things out to L3, so we'd rather
use that where possible.  It's also emulated via DATA_CACHE_FLUSH
on platforms where it isn't supported, so we can use it unconditionally.

We still use DATA_CACHE_FLUSH for invalidating the data cache, and to
flush the DC-tagged cachelines in L3 to be globally-observable.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>
This commit is contained in:
Kenneth Graunke 2021-08-24 18:09:53 -07:00 committed by Marge Bot
parent 1c8b4940eb
commit a969ad1ddf
2 changed files with 3 additions and 3 deletions
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4
src/gallium/drivers/iris/iris_pipe_control.c
View File

@ -195,7 +195,7 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch,
const uint32_t flush_bits[NUM_IRIS_DOMAINS] = {
[IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH,
[IRIS_DOMAIN_DEPTH_WRITE] = PIPE_CONTROL_DEPTH_CACHE_FLUSH,
[IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_DATA_CACHE_FLUSH,
[IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_FLUSH_HDC,
[IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE,
[IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,
[IRIS_DOMAIN_SAMPLER_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,
@ -205,7 +205,7 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch,
const uint32_t invalidate_bits[NUM_IRIS_DOMAINS] = {
[IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH,
[IRIS_DOMAIN_DEPTH_WRITE] = PIPE_CONTROL_DEPTH_CACHE_FLUSH,
[IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_DATA_CACHE_FLUSH,
[IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_FLUSH_HDC,
[IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE,
[IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_VF_CACHE_INVALIDATE,
[IRIS_DOMAIN_SAMPLER_READ] = PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE,

2
src/gallium/drivers/iris/iris_state.c
View File

@ -7640,7 +7640,7 @@ batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags)
if ((flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH))
iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_DEPTH_WRITE);
if ((flags & PIPE_CONTROL_DATA_CACHE_FLUSH))
if (flags & (PIPE_CONTROL_FLUSH_HDC | PIPE_CONTROL_DATA_CACHE_FLUSH))
iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_DATA_WRITE);
if ((flags & PIPE_CONTROL_FLUSH_ENABLE))