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intel/compiler: Fix A64 header construction with a uniform address 

fs_visitor::assign_curb_setup() maps UNIFORM registers to HW regs,
and contains the following assert:

            assert(inst->src[i].stride == 0);

emit_a64_oword_block_header's striding tricks run afoul of this
restriction, by producing stride 1 values on a 64-bit UNIFORM source.

Work around this by copying the UNIFORM value to a VGRF first.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16938>
This commit is contained in:
Kenneth Graunke 2022-06-08 15:25:35 -07:00 committed by Marge Bot
parent 30b57f10b3
commit a8e718c7e5
1 changed files with 12 additions and 2 deletions
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14
src/intel/compiler/brw_fs.cpp
View File

@ -6183,12 +6183,22 @@ static fs_reg
emit_a64_oword_block_header(const fs_builder &bld, const fs_reg &addr)
{
const fs_builder ubld = bld.exec_all().group(8, 0);
assert(type_sz(addr.type) == 8 && addr.stride == 0);
fs_reg expanded_addr = addr;
if (addr.file == UNIFORM) {
/* We can't do stride 1 with the UNIFORM file, it requires stride 0 */
expanded_addr = ubld.vgrf(BRW_REGISTER_TYPE_UQ);
expanded_addr.stride = 0;
ubld.MOV(expanded_addr, addr);
}
fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD);
ubld.MOV(header, brw_imm_ud(0));
/* Use a 2-wide MOV to fill out the address */
assert(type_sz(addr.type) == 8 && addr.stride == 0);
fs_reg addr_vec2 = addr;
fs_reg addr_vec2 = expanded_addr;
addr_vec2.type = BRW_REGISTER_TYPE_UD;
addr_vec2.stride = 1;
ubld.group(2, 0).MOV(header, addr_vec2);