radv: use a mask for VBOs and shaders prefetching
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
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@ -37,6 +37,20 @@
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#include "ac_debug.h"
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enum {
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RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
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RADV_PREFETCH_VS = (1 << 1),
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RADV_PREFETCH_TCS = (1 << 2),
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RADV_PREFETCH_TES = (1 << 3),
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RADV_PREFETCH_GS = (1 << 4),
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RADV_PREFETCH_PS = (1 << 5),
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RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
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RADV_PREFETCH_TCS |
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RADV_PREFETCH_TES |
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RADV_PREFETCH_GS |
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RADV_PREFETCH_PS)
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};
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static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
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struct radv_image *image,
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VkImageLayout src_layout,
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@ -617,17 +631,6 @@ radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
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si_cp_dma_prefetch(cmd_buffer, va, size);
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}
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static void
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radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
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{
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if (cmd_buffer->state.vb_prefetch_dirty) {
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radv_emit_prefetch_TC_L2_async(cmd_buffer,
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cmd_buffer->state.vb_va,
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cmd_buffer->state.vb_size);
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cmd_buffer->state.vb_prefetch_dirty = false;
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}
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}
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static void
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radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
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struct radv_shader_variant *shader)
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@ -649,18 +652,35 @@ static void
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radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
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struct radv_pipeline *pipeline)
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{
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struct radv_cmd_state *state = &cmd_buffer->state;
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if (state->prefetch_L2_mask & RADV_PREFETCH_VS)
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radv_emit_shader_prefetch(cmd_buffer,
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pipeline->shaders[MESA_SHADER_VERTEX]);
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radv_emit_VBO_descriptors_prefetch(cmd_buffer);
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if (state->prefetch_L2_mask & RADV_PREFETCH_VBO_DESCRIPTORS)
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radv_emit_prefetch_TC_L2_async(cmd_buffer, state->vb_va,
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state->vb_size);
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if (state->prefetch_L2_mask & RADV_PREFETCH_TCS)
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radv_emit_shader_prefetch(cmd_buffer,
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pipeline->shaders[MESA_SHADER_TESS_CTRL]);
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if (state->prefetch_L2_mask & RADV_PREFETCH_TES)
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radv_emit_shader_prefetch(cmd_buffer,
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pipeline->shaders[MESA_SHADER_TESS_EVAL]);
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if (state->prefetch_L2_mask & RADV_PREFETCH_GS) {
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radv_emit_shader_prefetch(cmd_buffer,
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pipeline->shaders[MESA_SHADER_GEOMETRY]);
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radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
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}
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if (state->prefetch_L2_mask & RADV_PREFETCH_PS)
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radv_emit_shader_prefetch(cmd_buffer,
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pipeline->shaders[MESA_SHADER_FRAGMENT]);
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state->prefetch_L2_mask = 0;
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}
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static void
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@ -1504,7 +1524,7 @@ radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bo
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cmd_buffer->state.vb_va = va;
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cmd_buffer->state.vb_size = count * 16;
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cmd_buffer->state.vb_prefetch_dirty = true;
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cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
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}
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cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
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@ -2310,6 +2330,9 @@ void radv_CmdBindPipeline(
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cmd_buffer->state.last_first_instance = -1;
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cmd_buffer->state.last_vertex_offset = -1;
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/* Prefetch all pipeline shaders at first draw time. */
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cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
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radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
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if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
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@ -3053,7 +3076,7 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer,
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* run in parallel, but starting the draw first is more
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* important.
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*/
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if (pipeline_is_dirty) {
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if (cmd_buffer->state.prefetch_L2_mask) {
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radv_emit_prefetch(cmd_buffer,
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cmd_buffer->state.pipeline);
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}
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@ -3063,7 +3086,7 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer,
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*/
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si_emit_cache_flush(cmd_buffer);
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if (pipeline_is_dirty) {
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if (cmd_buffer->state.prefetch_L2_mask) {
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radv_emit_prefetch(cmd_buffer,
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cmd_buffer->state.pipeline);
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}
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@ -915,13 +915,14 @@ struct radv_descriptor_state {
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struct radv_cmd_state {
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/* Vertex descriptors */
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bool vb_prefetch_dirty;
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uint64_t vb_va;
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unsigned vb_size;
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bool predicating;
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uint32_t dirty;
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uint32_t prefetch_L2_mask;
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struct radv_pipeline * pipeline;
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struct radv_pipeline * emitted_pipeline;
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struct radv_pipeline * compute_pipeline;
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