radv: fix various CMASK regressions on GFX9
This fixes a bunch of MSAA related CTS regressions. This restores previous behaviour on GFX9 but it should be fixed properly. Cc: 21.1 mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10374>
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@ -5991,11 +5991,8 @@ radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer, struct ra
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static uint32_t
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static uint32_t
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radv_init_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
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radv_init_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
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const VkImageSubresourceRange *range)
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const VkImageSubresourceRange *range, uint32_t value)
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{
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{
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static const uint32_t cmask_clear_values[4] = {0xffffffff, 0xdddddddd, 0xeeeeeeee, 0xffffffff};
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uint32_t log2_samples = util_logbase2(image->info.samples);
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uint32_t value = cmask_clear_values[log2_samples];
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struct radv_barrier_data barrier = {0};
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struct radv_barrier_data barrier = {0};
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barrier.layout_transitions.init_mask_ram = 1;
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barrier.layout_transitions.init_mask_ram = 1;
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@ -6079,7 +6076,26 @@ radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_i
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radv_src_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, image);
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radv_src_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, image);
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if (radv_image_has_cmask(image)) {
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if (radv_image_has_cmask(image)) {
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flush_bits |= radv_init_cmask(cmd_buffer, image, range);
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uint32_t value;
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if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
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/* TODO: Fix clearing CMASK layers on GFX9. */
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if (radv_image_is_tc_compat_cmask(image) ||
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(radv_image_has_fmask(image) &&
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radv_layout_can_fast_clear(cmd_buffer->device, image, dst_layout,
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dst_render_loop, dst_queue_mask))) {
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value = 0xccccccccu;
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} else {
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value = 0xffffffffu;
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}
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} else {
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static const uint32_t cmask_clear_values[4] = {0xffffffff, 0xdddddddd, 0xeeeeeeee, 0xffffffff};
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uint32_t log2_samples = util_logbase2(image->info.samples);
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value = cmask_clear_values[log2_samples];
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}
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flush_bits |= radv_init_cmask(cmd_buffer, image, range, value);
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}
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}
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if (radv_image_has_fmask(image)) {
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if (radv_image_has_fmask(image)) {
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@ -1242,11 +1242,17 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
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const VkImageSubresourceRange *range, uint32_t value)
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const VkImageSubresourceRange *range, uint32_t value)
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{
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{
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uint64_t offset = image->offset + image->planes[0].surface.cmask_offset;
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uint64_t offset = image->offset + image->planes[0].surface.cmask_offset;
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unsigned slice_size = image->planes[0].surface.cmask_slice_size;
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uint64_t size;
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uint64_t size;
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offset += slice_size * range->baseArrayLayer;
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if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
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size = slice_size * radv_get_layerCount(image, range);
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/* TODO: clear layers. */
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size = image->planes[0].surface.cmask_size;
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} else {
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unsigned slice_size = image->planes[0].surface.cmask_slice_size;
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offset += slice_size * range->baseArrayLayer;
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size = slice_size * radv_get_layerCount(image, range);
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}
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return radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value);
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return radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value);
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}
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}
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