panfrost/midgard: imov workaround
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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@ -1134,12 +1134,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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ALU_CASE(isub, isub);
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ALU_CASE(imul, imul);
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ALU_CASE(iabs, iabs);
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/* XXX: Use fmov, not imov for now, since NIR does not
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* differentiate well (it'll happily emits imov for floats,
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* which the hardware rather dislikes and breaks e.g
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* -bjellyfish */
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ALU_CASE(imov, fmov);
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ALU_CASE(imov, imov);
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ALU_CASE(feq32, feq);
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ALU_CASE(fne32, fne);
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@ -3236,6 +3231,31 @@ midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
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return progress;
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}
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/* We don't really understand the imov/fmov split, so always use fmov (but let
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* it be imov in the IR so we don't do unsafe floating point "optimizations"
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* and break things */
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static void
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midgard_imov_workaround(compiler_context *ctx, midgard_block *block)
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{
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mir_foreach_instr_in_block_safe(block, ins) {
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if (ins->type != TAG_ALU_4) continue;
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if (ins->alu.op != midgard_alu_op_imov) continue;
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ins->alu.op = midgard_alu_op_fmov;
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ins->alu.outmod = midgard_outmod_none;
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/* Remove flags that don't make sense */
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midgard_vector_alu_src s =
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vector_alu_from_unsigned(ins->alu.src2);
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s.mod = 0;
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ins->alu.src2 = vector_alu_srco_unsigned(s);
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}
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}
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/* The following passes reorder MIR instructions to enable better scheduling */
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static void
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@ -3487,6 +3507,7 @@ emit_block(compiler_context *ctx, nir_block *block)
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midgard_emit_store(ctx, this_block);
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midgard_pair_load_store(ctx, this_block);
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midgard_imov_workaround(ctx, this_block);
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/* Append fragment shader epilogue (value writeout) */
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if (ctx->stage == MESA_SHADER_FRAGMENT) {
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