st/mesa: set colormask to zero when blitting depth

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák 2012-07-09 02:23:22 +02:00
parent 5a74e17ab0
commit a7f3697eb8
2 changed files with 10 additions and 6 deletions

View File

@ -56,7 +56,7 @@ struct blit_state
struct pipe_context *pipe;
struct cso_context *cso;
struct pipe_blend_state blend;
struct pipe_blend_state blend_write_color, blend_keep_color;
struct pipe_depth_stencil_alpha_state depthstencil_keep;
struct pipe_depth_stencil_alpha_state depthstencil_write;
struct pipe_rasterizer_state rasterizer;
@ -94,7 +94,7 @@ util_create_blit(struct pipe_context *pipe, struct cso_context *cso)
ctx->cso = cso;
/* disabled blending/masking */
ctx->blend.rt[0].colormask = PIPE_MASK_RGBA;
ctx->blend_write_color.rt[0].colormask = PIPE_MASK_RGBA;
/* no-op depth/stencil/alpha */
ctx->depthstencil_write.depth.enabled = 1;
@ -564,7 +564,11 @@ util_blit_pixels(struct blit_state *ctx,
cso_save_vertex_buffers(ctx->cso);
/* set misc state we care about */
cso_set_blend(ctx->cso, &ctx->blend);
if (writemask)
cso_set_blend(ctx->cso, &ctx->blend_write_color);
else
cso_set_blend(ctx->cso, &ctx->blend_keep_color);
cso_set_depth_stencil_alpha(ctx->cso,
dst_is_depth ? &ctx->depthstencil_write :
&ctx->depthstencil_keep);
@ -721,7 +725,7 @@ util_blit_pixels_tex(struct blit_state *ctx,
cso_save_vertex_buffers(ctx->cso);
/* set misc state we care about */
cso_set_blend(ctx->cso, &ctx->blend);
cso_set_blend(ctx->cso, &ctx->blend_write_color);
cso_set_depth_stencil_alpha(ctx->cso, &ctx->depthstencil_keep);
cso_set_rasterizer(ctx->cso, &ctx->rasterizer);
cso_set_vertex_elements(ctx->cso, 2, ctx->velem);

View File

@ -294,7 +294,7 @@ st_BlitFramebuffer(struct gl_context *ctx,
srcX0, srcY0, srcX1, srcY1,
srcDepthRb->surface->u.tex.first_layer,
dstDepthSurf, dstX0, dstY0, dstX1, dstY1,
0.0, pFilter, TGSI_WRITEMASK_XYZW);
0.0, pFilter, 0);
}
else {
/* blitting depth and stencil separately */
@ -305,7 +305,7 @@ st_BlitFramebuffer(struct gl_context *ctx,
srcX0, srcY0, srcX1, srcY1,
srcDepthRb->surface->u.tex.first_layer,
dstDepthSurf, dstX0, dstY0, dstX1, dstY1,
0.0, pFilter, TGSI_WRITEMASK_XYZW);
0.0, pFilter, 0);
}
if (mask & GL_STENCIL_BUFFER_BIT) {