st/mesa: set colormask to zero when blitting depth
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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@ -56,7 +56,7 @@ struct blit_state
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struct pipe_context *pipe;
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struct cso_context *cso;
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struct pipe_blend_state blend;
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struct pipe_blend_state blend_write_color, blend_keep_color;
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struct pipe_depth_stencil_alpha_state depthstencil_keep;
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struct pipe_depth_stencil_alpha_state depthstencil_write;
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struct pipe_rasterizer_state rasterizer;
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@ -94,7 +94,7 @@ util_create_blit(struct pipe_context *pipe, struct cso_context *cso)
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ctx->cso = cso;
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/* disabled blending/masking */
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ctx->blend.rt[0].colormask = PIPE_MASK_RGBA;
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ctx->blend_write_color.rt[0].colormask = PIPE_MASK_RGBA;
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/* no-op depth/stencil/alpha */
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ctx->depthstencil_write.depth.enabled = 1;
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@ -564,7 +564,11 @@ util_blit_pixels(struct blit_state *ctx,
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cso_save_vertex_buffers(ctx->cso);
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/* set misc state we care about */
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cso_set_blend(ctx->cso, &ctx->blend);
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if (writemask)
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cso_set_blend(ctx->cso, &ctx->blend_write_color);
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else
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cso_set_blend(ctx->cso, &ctx->blend_keep_color);
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cso_set_depth_stencil_alpha(ctx->cso,
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dst_is_depth ? &ctx->depthstencil_write :
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&ctx->depthstencil_keep);
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@ -721,7 +725,7 @@ util_blit_pixels_tex(struct blit_state *ctx,
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cso_save_vertex_buffers(ctx->cso);
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/* set misc state we care about */
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cso_set_blend(ctx->cso, &ctx->blend);
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cso_set_blend(ctx->cso, &ctx->blend_write_color);
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cso_set_depth_stencil_alpha(ctx->cso, &ctx->depthstencil_keep);
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cso_set_rasterizer(ctx->cso, &ctx->rasterizer);
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cso_set_vertex_elements(ctx->cso, 2, ctx->velem);
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@ -294,7 +294,7 @@ st_BlitFramebuffer(struct gl_context *ctx,
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srcX0, srcY0, srcX1, srcY1,
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srcDepthRb->surface->u.tex.first_layer,
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dstDepthSurf, dstX0, dstY0, dstX1, dstY1,
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0.0, pFilter, TGSI_WRITEMASK_XYZW);
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0.0, pFilter, 0);
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}
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else {
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/* blitting depth and stencil separately */
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@ -305,7 +305,7 @@ st_BlitFramebuffer(struct gl_context *ctx,
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srcX0, srcY0, srcX1, srcY1,
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srcDepthRb->surface->u.tex.first_layer,
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dstDepthSurf, dstX0, dstY0, dstX1, dstY1,
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0.0, pFilter, TGSI_WRITEMASK_XYZW);
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0.0, pFilter, 0);
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}
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if (mask & GL_STENCIL_BUFFER_BIT) {
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