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freedreno/ir3: lower phi webs to regs 

nir's from_ssa pass is much better at avoiding inserting extra moves
than our logic is.  And lowering phi webs to regs just treats anything
involved in a phi web as an array of length=1.  Which with previous
array related fixes in RA/etc ends up working out quite well.  This cuts
down on extra instructions and also helps with register pressure.

Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark 2018-01-18 08:32:22 -05:00
parent 0a6ddf964f
commit a7ea2b4eba
1 changed files with 1 additions and 2 deletions
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3
src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
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@ -194,6 +194,7 @@ compile_init(struct ir3_compiler *compiler,
* in ir3_optimize_nir():
*/
NIR_PASS_V(ctx->s, nir_lower_locals_to_regs);
NIR_PASS_V(ctx->s, nir_convert_from_ssa, true);
if (fd_mesa_debug & FD_DBG_DISASM) {
DBG("dump nir%dv%d: type=%d, k={bp=%u,cts=%u,hp=%u}",
@ -907,8 +908,6 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
return;
}
compile_assert(ctx, alu->dest.dest.is_ssa);
/* General case: We can just grab the one used channel per src. */
for (int i = 0; i < info->num_inputs; i++) {
unsigned chan = ffs(alu->dest.write_mask) - 1;