r600: fix texcoords from constants
with some minor updates from Richard.
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08b7d32140
commit
a79eecb913
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@ -1149,41 +1149,49 @@ GLboolean tex_dst(r700_AssemblerBase *pAsm)
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GLboolean tex_src(r700_AssemblerBase *pAsm)
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{
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struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
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GLboolean bValidTexCoord = GL_FALSE;
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switch (pILInst->SrcReg[0].File)
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{
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switch (pILInst->SrcReg[0].File) {
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case PROGRAM_CONSTANT:
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case PROGRAM_LOCAL_PARAM:
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case PROGRAM_ENV_PARAM:
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case PROGRAM_STATE_VAR:
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bValidTexCoord = GL_TRUE;
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setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
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pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
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pAsm->S[0].src.reg = pAsm->aArgSubst[1];
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break;
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case PROGRAM_TEMPORARY:
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bValidTexCoord = GL_TRUE;
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pAsm->S[0].src.reg = pILInst->SrcReg[0].Index + pAsm->starting_temp_register_number;
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pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
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break;
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bValidTexCoord = GL_TRUE;
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pAsm->S[0].src.reg = pILInst->SrcReg[0].Index +
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pAsm->starting_temp_register_number;
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pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
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break;
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case PROGRAM_INPUT:
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switch (pILInst->SrcReg[0].Index)
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{
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case FRAG_ATTRIB_COL0:
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case FRAG_ATTRIB_COL1:
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case FRAG_ATTRIB_TEX0:
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case FRAG_ATTRIB_TEX1:
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case FRAG_ATTRIB_TEX2:
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case FRAG_ATTRIB_TEX3:
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case FRAG_ATTRIB_TEX4:
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case FRAG_ATTRIB_TEX5:
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case FRAG_ATTRIB_TEX6:
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case FRAG_ATTRIB_TEX7:
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bValidTexCoord = GL_TRUE;
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pAsm->S[0].src.reg = pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index];
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pAsm->S[0].src.rtype = SRC_REG_INPUT;
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}
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break;
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switch (pILInst->SrcReg[0].Index)
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{
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case FRAG_ATTRIB_COL0:
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case FRAG_ATTRIB_COL1:
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case FRAG_ATTRIB_TEX0:
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case FRAG_ATTRIB_TEX1:
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case FRAG_ATTRIB_TEX2:
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case FRAG_ATTRIB_TEX3:
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case FRAG_ATTRIB_TEX4:
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case FRAG_ATTRIB_TEX5:
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case FRAG_ATTRIB_TEX6:
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case FRAG_ATTRIB_TEX7:
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bValidTexCoord = GL_TRUE;
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pAsm->S[0].src.reg =
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pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index];
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pAsm->S[0].src.rtype = SRC_REG_INPUT;
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break;
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}
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break;
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}
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if(GL_TRUE == bValidTexCoord)
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{
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{
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setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
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}
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else
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@ -1201,7 +1209,7 @@ GLboolean tex_src(r700_AssemblerBase *pAsm)
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pAsm->S[0].src.negy = (pILInst->SrcReg[0].Negate >> 1) & 0x1;
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pAsm->S[0].src.negz = (pILInst->SrcReg[0].Negate >> 2) & 0x1;
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pAsm->S[0].src.negw = (pILInst->SrcReg[0].Negate >> 3) & 0x1;
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return GL_TRUE;
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}
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@ -2202,7 +2210,9 @@ GLboolean next_ins(r700_AssemblerBase *pAsm)
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{
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struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
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if( GL_TRUE == IsTex(pILInst->Opcode) )
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if( GL_TRUE == IsTex(pILInst->Opcode) &&
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/* handle const moves to temp register */
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!(pAsm->D.dst.opcode == SQ_OP2_INST_MOV) )
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{
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if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) {
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if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) )
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@ -3374,28 +3384,30 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
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case PROGRAM_ENV_PARAM:
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case PROGRAM_STATE_VAR:
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src_const = GL_TRUE;
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break;
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case PROGRAM_TEMPORARY:
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case PROGRAM_INPUT:
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src_const = GL_FALSE;
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break;
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}
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if (GL_TRUE == src_const)
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if (GL_TRUE == src_const)
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{
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radeon_error("TODO: Texture coordinates from a constant register not supported.\n");
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return GL_FALSE;
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if ( GL_FALSE == mov_temp(pAsm, 0) )
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return GL_FALSE;
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}
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switch (pAsm->pILInst[pAsm->uiCurInst].Opcode)
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switch (pAsm->pILInst[pAsm->uiCurInst].Opcode)
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{
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case OPCODE_TEX:
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pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE;
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pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE;
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break;
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case OPCODE_TXB:
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case OPCODE_TXB:
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radeon_error("do not support TXB yet\n");
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return GL_FALSE;
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break;
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case OPCODE_TXP:
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/* TODO : tex proj version : divid first 3 components by 4th */
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case OPCODE_TXP:
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/* TODO : tex proj version : divid first 3 components by 4th */
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pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE;
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break;
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default:
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@ -3418,13 +3430,13 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
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{
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return GL_FALSE;
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}
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if( GL_FALSE == tex_src(pAsm) )
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{
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return GL_FALSE;
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}
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if ( GL_FALSE == next_ins(pAsm) )
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if ( GL_FALSE == next_ins(pAsm) )
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{
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return GL_FALSE;
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}
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