radv: add support for local bos. (v3)
This uses the new kernel interfaces for reduced cs overhead, We only set the local flag for memory allocations that don't have a dedicated allocation and ones that aren't imports. v2: add to all the internal buffer creation paths. v3: missed some command submission paths, handle 0/empty bo lists. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
39c5c12f8f
commit
a639d40f13
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@ -313,7 +313,8 @@ radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
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bo = device->ws->buffer_create(device->ws,
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new_size, 4096,
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RADEON_DOMAIN_GTT,
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RADEON_FLAG_CPU_ACCESS);
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RADEON_FLAG_CPU_ACCESS|
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RADEON_FLAG_NO_INTERPROCESS_SHARING);
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if (!bo) {
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cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
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@ -61,7 +61,8 @@ radv_init_trace(struct radv_device *device)
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device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
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RADEON_DOMAIN_VRAM,
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RADEON_FLAG_CPU_ACCESS);
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RADEON_FLAG_CPU_ACCESS|
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RADEON_FLAG_NO_INTERPROCESS_SHARING);
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if (!device->trace_bo)
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return false;
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@ -431,7 +431,7 @@ VkResult radv_CreateDescriptorPool(
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if (bo_size) {
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pool->bo = device->ws->buffer_create(device->ws, bo_size,
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32, RADEON_DOMAIN_VRAM, 0);
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32, RADEON_DOMAIN_VRAM, RADEON_FLAG_NO_INTERPROCESS_SHARING);
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pool->mapped_ptr = (uint8_t*)device->ws->buffer_map(pool->bo);
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}
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pool->size = bo_size;
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@ -1394,6 +1394,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
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unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
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unsigned max_offchip_buffers;
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unsigned hs_offchip_param = 0;
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uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
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if (!queue->has_tess_rings) {
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if (needs_tess_rings)
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add_tess_rings = true;
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@ -1427,7 +1428,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
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scratch_size,
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4096,
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RADEON_DOMAIN_VRAM,
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RADEON_FLAG_NO_CPU_ACCESS);
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ring_bo_flags);
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if (!scratch_bo)
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goto fail;
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} else
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@ -1438,7 +1439,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
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compute_scratch_size,
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4096,
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RADEON_DOMAIN_VRAM,
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RADEON_FLAG_NO_CPU_ACCESS);
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ring_bo_flags);
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if (!compute_scratch_bo)
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goto fail;
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@ -1450,7 +1451,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
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esgs_ring_size,
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4096,
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RADEON_DOMAIN_VRAM,
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RADEON_FLAG_NO_CPU_ACCESS);
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ring_bo_flags);
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if (!esgs_ring_bo)
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goto fail;
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} else {
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@ -1463,7 +1464,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
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gsvs_ring_size,
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4096,
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RADEON_DOMAIN_VRAM,
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RADEON_FLAG_NO_CPU_ACCESS);
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ring_bo_flags);
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if (!gsvs_ring_bo)
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goto fail;
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} else {
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@ -1476,14 +1477,14 @@ radv_get_preamble_cs(struct radv_queue *queue,
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tess_factor_ring_size,
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256,
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RADEON_DOMAIN_VRAM,
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RADEON_FLAG_NO_CPU_ACCESS);
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ring_bo_flags);
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if (!tess_factor_ring_bo)
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goto fail;
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tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
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tess_offchip_ring_size,
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256,
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RADEON_DOMAIN_VRAM,
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RADEON_FLAG_NO_CPU_ACCESS);
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ring_bo_flags);
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if (!tess_offchip_ring_bo)
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goto fail;
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} else {
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@ -1510,7 +1511,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
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size,
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4096,
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RADEON_DOMAIN_VRAM,
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RADEON_FLAG_CPU_ACCESS);
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RADEON_FLAG_CPU_ACCESS|RADEON_FLAG_NO_INTERPROCESS_SHARING);
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if (!descriptor_bo)
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goto fail;
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} else
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@ -2119,6 +2120,9 @@ VkResult radv_alloc_memory(VkDevice _device,
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if (mem_flags & RADV_MEM_IMPLICIT_SYNC)
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flags |= RADEON_FLAG_IMPLICIT_SYNC;
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if (!dedicate_info && !import_info)
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flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
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mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
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domain, flags);
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@ -2682,7 +2686,7 @@ VkResult radv_CreateEvent(
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event->bo = device->ws->buffer_create(device->ws, 8, 8,
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RADEON_DOMAIN_GTT,
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RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS);
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RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
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if (!event->bo) {
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vk_free2(&device->alloc, pAllocator, event);
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return VK_ERROR_OUT_OF_DEVICE_MEMORY;
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@ -780,7 +780,7 @@ VkResult radv_CreateQueryPool(
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size += 4 * pCreateInfo->queryCount;
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pool->bo = device->ws->buffer_create(device->ws, size,
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64, RADEON_DOMAIN_GTT, 0);
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64, RADEON_DOMAIN_GTT, RADEON_FLAG_NO_INTERPROCESS_SHARING);
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if (!pool->bo) {
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vk_free2(&device->alloc, pAllocator, pool);
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@ -54,6 +54,7 @@ enum radeon_bo_flag { /* bitfield */
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RADEON_FLAG_VIRTUAL = (1 << 3),
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RADEON_FLAG_VA_UNCACHED = (1 << 4),
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RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
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RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
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};
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enum radeon_bo_usage { /* bitfield */
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@ -325,7 +325,7 @@ radv_alloc_shader_memory(struct radv_device *device,
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slab->size = 256 * 1024;
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slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
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RADEON_DOMAIN_VRAM, 0);
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RADEON_DOMAIN_VRAM, RADEON_FLAG_NO_INTERPROCESS_SHARING);
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slab->ptr = (char*)device->ws->buffer_map(slab->bo);
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list_inithead(&slab->shaders);
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@ -571,7 +571,8 @@ cik_create_gfx_config(struct radv_device *device)
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device->gfx_init = device->ws->buffer_create(device->ws,
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cs->cdw * 4, 4096,
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RADEON_DOMAIN_GTT,
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RADEON_FLAG_CPU_ACCESS);
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RADEON_FLAG_CPU_ACCESS|
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RADEON_FLAG_NO_INTERPROCESS_SHARING);
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if (!device->gfx_init)
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goto fail;
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@ -332,6 +332,10 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
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request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
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if (!(flags & RADEON_FLAG_IMPLICIT_SYNC) && ws->info.drm_minor >= 22)
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request.flags |= AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
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if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING && ws->info.drm_minor >= 20) {
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bo->is_local = true;
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request.flags |= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID;
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}
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/* this won't do anything on pre 4.9 kernels */
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if (ws->zero_all_vram_allocs && (initial_domain & RADEON_DOMAIN_VRAM))
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@ -45,6 +45,7 @@ struct radv_amdgpu_winsys_bo {
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uint64_t size;
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struct radv_amdgpu_winsys *ws;
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bool is_virtual;
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bool is_local;
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int ref_count;
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union {
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@ -202,7 +202,8 @@ radv_amdgpu_cs_create(struct radeon_winsys *ws,
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if (cs->ws->use_ib_bos) {
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cs->ib_buffer = ws->buffer_create(ws, ib_size, 0,
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RADEON_DOMAIN_GTT,
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RADEON_FLAG_CPU_ACCESS);
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RADEON_FLAG_CPU_ACCESS|
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RADEON_FLAG_NO_INTERPROCESS_SHARING);
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if (!cs->ib_buffer) {
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free(cs);
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return NULL;
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@ -287,7 +288,8 @@ static void radv_amdgpu_cs_grow(struct radeon_winsys_cs *_cs, size_t min_size)
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cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0,
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RADEON_DOMAIN_GTT,
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RADEON_FLAG_CPU_ACCESS);
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RADEON_FLAG_CPU_ACCESS|
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RADEON_FLAG_NO_INTERPROCESS_SHARING);
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if (!cs->ib_buffer) {
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cs->base.cdw = 0;
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@ -471,6 +473,9 @@ static void radv_amdgpu_cs_add_buffer(struct radeon_winsys_cs *_cs,
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return;
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}
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if (bo->is_local)
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return;
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radv_amdgpu_cs_add_buffer_internal(cs, bo->bo, priority);
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}
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@ -541,6 +546,10 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
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} else if (count == 1 && !extra_bo && !extra_cs &&
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!radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
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struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
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if (cs->num_buffers == 0) {
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*bo_list = 0;
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return 0;
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}
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r = amdgpu_bo_list_create(ws->dev, cs->num_buffers, cs->handles,
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cs->priorities, bo_list);
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} else {
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@ -556,7 +565,10 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
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if (extra_cs) {
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total_buffer_count += ((struct radv_amdgpu_cs*)extra_cs)->num_buffers;
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}
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if (total_buffer_count == 0) {
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*bo_list = 0;
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return 0;
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}
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amdgpu_bo_handle *handles = malloc(sizeof(amdgpu_bo_handle) * total_buffer_count);
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uint8_t *priorities = malloc(sizeof(uint8_t) * total_buffer_count);
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if (!handles || !priorities) {
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@ -721,6 +733,7 @@ static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
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"see dmesg for more information.\n");
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}
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if (bo_list)
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amdgpu_bo_list_destroy(bo_list);
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if (fence)
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@ -795,6 +808,7 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
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"see dmesg for more information.\n");
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}
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if (bo_list)
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amdgpu_bo_list_destroy(bo_list);
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if (r)
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@ -856,7 +870,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
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}
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assert(cnt);
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bo = ws->buffer_create(ws, 4 * size, 4096, RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
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bo = ws->buffer_create(ws, 4 * size, 4096, RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS|RADEON_FLAG_NO_INTERPROCESS_SHARING);
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ptr = ws->buffer_map(bo);
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if (preamble_cs) {
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@ -905,6 +919,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
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"see dmesg for more information.\n");
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}
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if (bo_list)
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amdgpu_bo_list_destroy(bo_list);
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ws->buffer_destroy(bo);
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@ -1038,7 +1053,8 @@ static struct radeon_winsys_ctx *radv_amdgpu_ctx_create(struct radeon_winsys *_w
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assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
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ctx->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8,
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RADEON_DOMAIN_GTT,
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RADEON_FLAG_CPU_ACCESS);
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RADEON_FLAG_CPU_ACCESS|
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RADEON_FLAG_NO_INTERPROCESS_SHARING);
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if (ctx->fence_bo)
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ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo);
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if (ctx->fence_map)
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