vc4: Move the QPU instructions to schedule into each block.
We'll want to schedule them individually, to handle delay slots.
This commit is contained in:
parent
37ecc61662
commit
a59da513d3
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@ -536,6 +536,7 @@ qir_new_block(struct vc4_compile *c)
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struct qblock *block = rzalloc(c, struct qblock);
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struct qblock *block = rzalloc(c, struct qblock);
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list_inithead(&block->instructions);
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list_inithead(&block->instructions);
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list_inithead(&block->qpu_inst_list);
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block->predecessors = _mesa_set_create(block,
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block->predecessors = _mesa_set_create(block,
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_mesa_hash_pointer,
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_mesa_hash_pointer,
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@ -355,6 +355,7 @@ struct qblock {
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struct list_head link;
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struct list_head link;
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struct list_head instructions;
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struct list_head instructions;
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struct list_head qpu_inst_list;
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struct set *predecessors;
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struct set *predecessors;
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struct qblock *successors[2];
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struct qblock *successors[2];
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@ -467,6 +468,7 @@ struct vc4_compile {
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struct qblock *loop_break_block;
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struct qblock *loop_break_block;
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struct list_head qpu_inst_list;
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struct list_head qpu_inst_list;
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uint64_t *qpu_insts;
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uint64_t *qpu_insts;
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uint32_t qpu_inst_count;
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uint32_t qpu_inst_count;
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uint32_t qpu_inst_size;
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uint32_t qpu_inst_size;
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@ -44,31 +44,31 @@ vc4_dump_program(struct vc4_compile *c)
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}
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}
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static void
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static void
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queue(struct vc4_compile *c, uint64_t inst)
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queue(struct qblock *block, uint64_t inst)
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{
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{
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struct queued_qpu_inst *q = rzalloc(c, struct queued_qpu_inst);
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struct queued_qpu_inst *q = rzalloc(block, struct queued_qpu_inst);
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q->inst = inst;
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q->inst = inst;
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list_addtail(&q->link, &c->qpu_inst_list);
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list_addtail(&q->link, &block->qpu_inst_list);
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}
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}
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static uint64_t *
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static uint64_t *
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last_inst(struct vc4_compile *c)
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last_inst(struct qblock *block)
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{
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{
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struct queued_qpu_inst *q =
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struct queued_qpu_inst *q =
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(struct queued_qpu_inst *)c->qpu_inst_list.prev;
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(struct queued_qpu_inst *)block->qpu_inst_list.prev;
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return &q->inst;
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return &q->inst;
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}
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}
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static void
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static void
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set_last_cond_add(struct vc4_compile *c, uint32_t cond)
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set_last_cond_add(struct qblock *block, uint32_t cond)
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{
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{
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*last_inst(c) = qpu_set_cond_add(*last_inst(c), cond);
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*last_inst(block) = qpu_set_cond_add(*last_inst(block), cond);
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}
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}
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static void
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static void
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set_last_cond_mul(struct vc4_compile *c, uint32_t cond)
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set_last_cond_mul(struct qblock *block, uint32_t cond)
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{
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{
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*last_inst(c) = qpu_set_cond_mul(*last_inst(c), cond);
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*last_inst(block) = qpu_set_cond_mul(*last_inst(block), cond);
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}
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}
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/**
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/**
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@ -106,7 +106,7 @@ swap_file(struct qpu_reg *src)
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* instruction, instead. We reserve ra31/rb31 for this purpose.
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* instruction, instead. We reserve ra31/rb31 for this purpose.
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*/
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*/
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static void
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static void
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fixup_raddr_conflict(struct vc4_compile *c,
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fixup_raddr_conflict(struct qblock *block,
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struct qpu_reg dst,
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struct qpu_reg dst,
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struct qpu_reg *src0, struct qpu_reg *src1,
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struct qpu_reg *src0, struct qpu_reg *src1,
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struct qinst *inst, uint64_t *unpack)
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struct qinst *inst, uint64_t *unpack)
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@ -129,39 +129,39 @@ fixup_raddr_conflict(struct vc4_compile *c,
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* in case of unpacks.
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* in case of unpacks.
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*/
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*/
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if (qir_is_float_input(inst))
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if (qir_is_float_input(inst))
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queue(c, qpu_a_FMAX(qpu_rb(31), *src0, *src0));
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queue(block, qpu_a_FMAX(qpu_rb(31), *src0, *src0));
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else
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else
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queue(c, qpu_a_MOV(qpu_rb(31), *src0));
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queue(block, qpu_a_MOV(qpu_rb(31), *src0));
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/* If we had an unpack on this A-file source, we need to put
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/* If we had an unpack on this A-file source, we need to put
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* it into this MOV, not into the later move from regfile B.
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* it into this MOV, not into the later move from regfile B.
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*/
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*/
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if (inst->src[0].pack) {
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if (inst->src[0].pack) {
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*last_inst(c) |= *unpack;
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*last_inst(block) |= *unpack;
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*unpack = 0;
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*unpack = 0;
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}
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}
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*src0 = qpu_rb(31);
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*src0 = qpu_rb(31);
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} else {
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} else {
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queue(c, qpu_a_MOV(qpu_ra(31), *src0));
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queue(block, qpu_a_MOV(qpu_ra(31), *src0));
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*src0 = qpu_ra(31);
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*src0 = qpu_ra(31);
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}
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}
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}
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}
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static void
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static void
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set_last_dst_pack(struct vc4_compile *c, struct qinst *inst)
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set_last_dst_pack(struct qblock *block, struct qinst *inst)
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{
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{
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bool had_pm = *last_inst(c) & QPU_PM;
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bool had_pm = *last_inst(block) & QPU_PM;
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bool had_ws = *last_inst(c) & QPU_WS;
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bool had_ws = *last_inst(block) & QPU_WS;
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uint32_t unpack = QPU_GET_FIELD(*last_inst(c), QPU_UNPACK);
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uint32_t unpack = QPU_GET_FIELD(*last_inst(block), QPU_UNPACK);
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if (!inst->dst.pack)
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if (!inst->dst.pack)
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return;
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return;
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*last_inst(c) |= QPU_SET_FIELD(inst->dst.pack, QPU_PACK);
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*last_inst(block) |= QPU_SET_FIELD(inst->dst.pack, QPU_PACK);
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if (qir_is_mul(inst)) {
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if (qir_is_mul(inst)) {
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assert(!unpack || had_pm);
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assert(!unpack || had_pm);
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*last_inst(c) |= QPU_PM;
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*last_inst(block) |= QPU_PM;
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} else {
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} else {
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assert(!unpack || !had_pm);
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assert(!unpack || !had_pm);
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assert(!had_ws); /* dst must be a-file to pack. */
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assert(!had_ws); /* dst must be a-file to pack. */
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@ -169,51 +169,23 @@ set_last_dst_pack(struct vc4_compile *c, struct qinst *inst)
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}
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}
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static void
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static void
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handle_r4_qpu_write(struct vc4_compile *c, struct qinst *qinst,
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handle_r4_qpu_write(struct qblock *block, struct qinst *qinst,
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struct qpu_reg dst)
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struct qpu_reg dst)
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{
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{
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if (dst.mux != QPU_MUX_R4)
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if (dst.mux != QPU_MUX_R4)
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queue(c, qpu_a_MOV(dst, qpu_r4()));
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queue(block, qpu_a_MOV(dst, qpu_r4()));
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else if (qinst->sf)
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else if (qinst->sf)
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queue(c, qpu_a_MOV(qpu_ra(QPU_W_NOP), qpu_r4()));
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queue(block, qpu_a_MOV(qpu_ra(QPU_W_NOP), qpu_r4()));
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}
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}
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void
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static void
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vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
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vc4_generate_code_block(struct vc4_compile *c,
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struct qblock *block,
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struct qpu_reg *temp_registers)
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{
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{
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struct qpu_reg *temp_registers = vc4_register_allocate(vc4, c);
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uint32_t inputs_remaining = c->num_inputs;
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uint32_t vpm_read_fifo_count = 0;
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uint32_t vpm_read_offset = 0;
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int last_vpm_read_index = -1;
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int last_vpm_read_index = -1;
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list_inithead(&c->qpu_inst_list);
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qir_for_each_inst(qinst, block) {
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switch (c->stage) {
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case QSTAGE_VERT:
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case QSTAGE_COORD:
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/* There's a 4-entry FIFO for VPMVCD reads, each of which can
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* load up to 16 dwords (4 vec4s) per vertex.
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*/
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while (inputs_remaining) {
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uint32_t num_entries = MIN2(inputs_remaining, 16);
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queue(c, qpu_load_imm_ui(qpu_vrsetup(),
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vpm_read_offset |
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0x00001a00 |
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((num_entries & 0xf) << 20)));
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inputs_remaining -= num_entries;
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vpm_read_offset += num_entries;
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vpm_read_fifo_count++;
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}
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assert(vpm_read_fifo_count <= 4);
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queue(c, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
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break;
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case QSTAGE_FRAG:
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break;
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}
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qir_for_each_inst_inorder(qinst, c) {
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#if 0
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#if 0
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fprintf(stderr, "translating qinst to qpu: ");
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fprintf(stderr, "translating qinst to qpu: ");
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qir_dump_inst(qinst);
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qir_dump_inst(qinst);
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@ -369,40 +341,40 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
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case QOP_LOG2:
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case QOP_LOG2:
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switch (qinst->op) {
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switch (qinst->op) {
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case QOP_RCP:
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case QOP_RCP:
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queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
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queue(block, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
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src[0]) | unpack);
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src[0]) | unpack);
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break;
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break;
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case QOP_RSQ:
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case QOP_RSQ:
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queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT),
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queue(block, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT),
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src[0]) | unpack);
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src[0]) | unpack);
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break;
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break;
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case QOP_EXP2:
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case QOP_EXP2:
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queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP),
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queue(block, qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP),
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src[0]) | unpack);
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src[0]) | unpack);
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break;
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break;
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case QOP_LOG2:
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case QOP_LOG2:
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queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG),
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queue(block, qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG),
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src[0]) | unpack);
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src[0]) | unpack);
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break;
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break;
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default:
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default:
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abort();
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abort();
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}
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}
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handle_r4_qpu_write(c, qinst, dst);
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handle_r4_qpu_write(block, qinst, dst);
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break;
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break;
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case QOP_LOAD_IMM:
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case QOP_LOAD_IMM:
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assert(qinst->src[0].file == QFILE_LOAD_IMM);
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assert(qinst->src[0].file == QFILE_LOAD_IMM);
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queue(c, qpu_load_imm_ui(dst, qinst->src[0].index));
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queue(block, qpu_load_imm_ui(dst, qinst->src[0].index));
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break;
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break;
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case QOP_MS_MASK:
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case QOP_MS_MASK:
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src[1] = qpu_ra(QPU_R_MS_REV_FLAGS);
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src[1] = qpu_ra(QPU_R_MS_REV_FLAGS);
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fixup_raddr_conflict(c, dst, &src[0], &src[1],
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fixup_raddr_conflict(block, dst, &src[0], &src[1],
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qinst, &unpack);
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qinst, &unpack);
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queue(c, qpu_a_AND(qpu_ra(QPU_W_MS_FLAGS),
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queue(block, qpu_a_AND(qpu_ra(QPU_W_MS_FLAGS),
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src[0], src[1]) | unpack);
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src[0], src[1]) | unpack);
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break;
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break;
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case QOP_FRAG_Z:
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case QOP_FRAG_Z:
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@ -413,45 +385,45 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
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break;
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break;
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case QOP_TLB_COLOR_READ:
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case QOP_TLB_COLOR_READ:
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queue(c, qpu_NOP());
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queue(block, qpu_NOP());
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*last_inst(c) = qpu_set_sig(*last_inst(c),
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*last_inst(block) = qpu_set_sig(*last_inst(block),
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QPU_SIG_COLOR_LOAD);
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QPU_SIG_COLOR_LOAD);
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handle_r4_qpu_write(c, qinst, dst);
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handle_r4_qpu_write(block, qinst, dst);
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break;
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break;
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case QOP_VARY_ADD_C:
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case QOP_VARY_ADD_C:
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queue(c, qpu_a_FADD(dst, src[0], qpu_r5()) | unpack);
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queue(block, qpu_a_FADD(dst, src[0], qpu_r5()) | unpack);
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break;
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break;
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case QOP_TEX_S:
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case QOP_TEX_S:
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case QOP_TEX_T:
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case QOP_TEX_T:
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case QOP_TEX_R:
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case QOP_TEX_R:
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case QOP_TEX_B:
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case QOP_TEX_B:
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queue(c, qpu_a_MOV(qpu_rb(QPU_W_TMU0_S +
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queue(block, qpu_a_MOV(qpu_rb(QPU_W_TMU0_S +
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(qinst->op - QOP_TEX_S)),
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(qinst->op - QOP_TEX_S)),
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src[0]) | unpack);
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src[0]) | unpack);
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break;
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break;
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case QOP_TEX_DIRECT:
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case QOP_TEX_DIRECT:
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fixup_raddr_conflict(c, dst, &src[0], &src[1],
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fixup_raddr_conflict(block, dst, &src[0], &src[1],
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qinst, &unpack);
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qinst, &unpack);
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queue(c, qpu_a_ADD(qpu_rb(QPU_W_TMU0_S),
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queue(block, qpu_a_ADD(qpu_rb(QPU_W_TMU0_S),
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src[0], src[1]) | unpack);
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src[0], src[1]) | unpack);
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break;
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break;
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case QOP_TEX_RESULT:
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case QOP_TEX_RESULT:
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queue(c, qpu_NOP());
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queue(block, qpu_NOP());
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*last_inst(c) = qpu_set_sig(*last_inst(c),
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*last_inst(block) = qpu_set_sig(*last_inst(block),
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QPU_SIG_LOAD_TMU0);
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QPU_SIG_LOAD_TMU0);
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handle_r4_qpu_write(c, qinst, dst);
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handle_r4_qpu_write(block, qinst, dst);
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break;
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break;
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case QOP_BRANCH:
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case QOP_BRANCH:
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/* The branch target will be updated at QPU scheduling
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/* The branch target will be updated at QPU scheduling
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* time.
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* time.
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*/
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*/
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queue(c, (qpu_branch(qinst->cond, 0) |
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queue(block, (qpu_branch(qinst->cond, 0) |
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QPU_BRANCH_REL));
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QPU_BRANCH_REL));
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handled_qinst_cond = true;
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handled_qinst_cond = true;
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break;
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break;
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@ -472,22 +444,22 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
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if (qir_get_op_nsrc(qinst->op) == 1)
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if (qir_get_op_nsrc(qinst->op) == 1)
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src[1] = src[0];
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src[1] = src[0];
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fixup_raddr_conflict(c, dst, &src[0], &src[1],
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fixup_raddr_conflict(block, dst, &src[0], &src[1],
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qinst, &unpack);
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qinst, &unpack);
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if (qir_is_mul(qinst)) {
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if (qir_is_mul(qinst)) {
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queue(c, qpu_m_alu2(translate[qinst->op].op,
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queue(block, qpu_m_alu2(translate[qinst->op].op,
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dst,
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dst,
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src[0], src[1]) | unpack);
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src[0], src[1]) | unpack);
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set_last_cond_mul(c, qinst->cond);
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set_last_cond_mul(block, qinst->cond);
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} else {
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} else {
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queue(c, qpu_a_alu2(translate[qinst->op].op,
|
queue(block, qpu_a_alu2(translate[qinst->op].op,
|
||||||
dst,
|
dst,
|
||||||
src[0], src[1]) | unpack);
|
src[0], src[1]) | unpack);
|
||||||
set_last_cond_add(c, qinst->cond);
|
set_last_cond_add(block, qinst->cond);
|
||||||
}
|
}
|
||||||
handled_qinst_cond = true;
|
handled_qinst_cond = true;
|
||||||
set_last_dst_pack(c, qinst);
|
set_last_dst_pack(block, qinst);
|
||||||
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -496,8 +468,47 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
|
||||||
handled_qinst_cond);
|
handled_qinst_cond);
|
||||||
|
|
||||||
if (qinst->sf)
|
if (qinst->sf)
|
||||||
*last_inst(c) |= QPU_SF;
|
*last_inst(block) |= QPU_SF;
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
|
||||||
|
{
|
||||||
|
struct qpu_reg *temp_registers = vc4_register_allocate(vc4, c);
|
||||||
|
uint32_t inputs_remaining = c->num_inputs;
|
||||||
|
uint32_t vpm_read_fifo_count = 0;
|
||||||
|
uint32_t vpm_read_offset = 0;
|
||||||
|
struct qblock *start_block = list_first_entry(&c->blocks,
|
||||||
|
struct qblock, link);
|
||||||
|
|
||||||
|
switch (c->stage) {
|
||||||
|
case QSTAGE_VERT:
|
||||||
|
case QSTAGE_COORD:
|
||||||
|
/* There's a 4-entry FIFO for VPMVCD reads, each of which can
|
||||||
|
* load up to 16 dwords (4 vec4s) per vertex.
|
||||||
|
*/
|
||||||
|
while (inputs_remaining) {
|
||||||
|
uint32_t num_entries = MIN2(inputs_remaining, 16);
|
||||||
|
queue(start_block,
|
||||||
|
qpu_load_imm_ui(qpu_vrsetup(),
|
||||||
|
vpm_read_offset |
|
||||||
|
0x00001a00 |
|
||||||
|
((num_entries & 0xf) << 20)));
|
||||||
|
inputs_remaining -= num_entries;
|
||||||
|
vpm_read_offset += num_entries;
|
||||||
|
vpm_read_fifo_count++;
|
||||||
|
}
|
||||||
|
assert(vpm_read_fifo_count <= 4);
|
||||||
|
|
||||||
|
queue(start_block, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
|
||||||
|
break;
|
||||||
|
case QSTAGE_FRAG:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
qir_for_each_block(block, c)
|
||||||
|
vc4_generate_code_block(c, block, temp_registers);
|
||||||
|
|
||||||
uint32_t cycles = qpu_schedule_instructions(c);
|
uint32_t cycles = qpu_schedule_instructions(c);
|
||||||
uint32_t inst_count_at_schedule_time = c->qpu_inst_count;
|
uint32_t inst_count_at_schedule_time = c->qpu_inst_count;
|
||||||
|
|
|
@ -722,22 +722,14 @@ mark_instruction_scheduled(struct list_head *schedule_list,
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t
|
static uint32_t
|
||||||
schedule_instructions(struct vc4_compile *c, struct list_head *schedule_list)
|
schedule_instructions(struct vc4_compile *c, struct list_head *schedule_list,
|
||||||
|
enum quniform_contents *orig_uniform_contents,
|
||||||
|
uint32_t *orig_uniform_data,
|
||||||
|
uint32_t *next_uniform)
|
||||||
{
|
{
|
||||||
struct choose_scoreboard scoreboard;
|
struct choose_scoreboard scoreboard;
|
||||||
uint32_t time = 0;
|
uint32_t time = 0;
|
||||||
|
|
||||||
/* We reorder the uniforms as we schedule instructions, so save the
|
|
||||||
* old data off and replace it.
|
|
||||||
*/
|
|
||||||
uint32_t *uniform_data = c->uniform_data;
|
|
||||||
enum quniform_contents *uniform_contents = c->uniform_contents;
|
|
||||||
c->uniform_contents = ralloc_array(c, enum quniform_contents,
|
|
||||||
c->num_uniforms);
|
|
||||||
c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
|
|
||||||
c->uniform_array_size = c->num_uniforms;
|
|
||||||
uint32_t next_uniform = 0;
|
|
||||||
|
|
||||||
memset(&scoreboard, 0, sizeof(scoreboard));
|
memset(&scoreboard, 0, sizeof(scoreboard));
|
||||||
scoreboard.last_waddr_a = ~0;
|
scoreboard.last_waddr_a = ~0;
|
||||||
scoreboard.last_waddr_b = ~0;
|
scoreboard.last_waddr_b = ~0;
|
||||||
|
@ -785,11 +777,11 @@ schedule_instructions(struct vc4_compile *c, struct list_head *schedule_list)
|
||||||
mark_instruction_scheduled(schedule_list, time,
|
mark_instruction_scheduled(schedule_list, time,
|
||||||
chosen, true);
|
chosen, true);
|
||||||
if (chosen->uniform != -1) {
|
if (chosen->uniform != -1) {
|
||||||
c->uniform_data[next_uniform] =
|
c->uniform_data[*next_uniform] =
|
||||||
uniform_data[chosen->uniform];
|
orig_uniform_data[chosen->uniform];
|
||||||
c->uniform_contents[next_uniform] =
|
c->uniform_contents[*next_uniform] =
|
||||||
uniform_contents[chosen->uniform];
|
orig_uniform_contents[chosen->uniform];
|
||||||
next_uniform++;
|
(*next_uniform)++;
|
||||||
}
|
}
|
||||||
|
|
||||||
merge = choose_instruction_to_schedule(&scoreboard,
|
merge = choose_instruction_to_schedule(&scoreboard,
|
||||||
|
@ -801,11 +793,11 @@ schedule_instructions(struct vc4_compile *c, struct list_head *schedule_list)
|
||||||
inst = qpu_merge_inst(inst, merge->inst->inst);
|
inst = qpu_merge_inst(inst, merge->inst->inst);
|
||||||
assert(inst != 0);
|
assert(inst != 0);
|
||||||
if (merge->uniform != -1) {
|
if (merge->uniform != -1) {
|
||||||
c->uniform_data[next_uniform] =
|
c->uniform_data[*next_uniform] =
|
||||||
uniform_data[merge->uniform];
|
orig_uniform_data[merge->uniform];
|
||||||
c->uniform_contents[next_uniform] =
|
c->uniform_contents[*next_uniform] =
|
||||||
uniform_contents[merge->uniform];
|
orig_uniform_contents[merge->uniform];
|
||||||
next_uniform++;
|
(*next_uniform)++;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (debug) {
|
if (debug) {
|
||||||
|
@ -840,47 +832,37 @@ schedule_instructions(struct vc4_compile *c, struct list_head *schedule_list)
|
||||||
time++;
|
time++;
|
||||||
}
|
}
|
||||||
|
|
||||||
assert(next_uniform == c->num_uniforms);
|
|
||||||
|
|
||||||
return time;
|
return time;
|
||||||
}
|
}
|
||||||
|
|
||||||
uint32_t
|
static uint32_t
|
||||||
qpu_schedule_instructions(struct vc4_compile *c)
|
qpu_schedule_instructions_block(struct vc4_compile *c, struct qblock *block,
|
||||||
|
enum quniform_contents *orig_uniform_contents,
|
||||||
|
uint32_t *orig_uniform_data,
|
||||||
|
uint32_t *next_uniform)
|
||||||
{
|
{
|
||||||
void *mem_ctx = ralloc_context(NULL);
|
void *mem_ctx = ralloc_context(NULL);
|
||||||
struct list_head schedule_list;
|
struct list_head schedule_list;
|
||||||
|
|
||||||
list_inithead(&schedule_list);
|
list_inithead(&schedule_list);
|
||||||
|
|
||||||
if (debug) {
|
|
||||||
fprintf(stderr, "Pre-schedule instructions\n");
|
|
||||||
list_for_each_entry(struct queued_qpu_inst, q,
|
|
||||||
&c->qpu_inst_list, link) {
|
|
||||||
vc4_qpu_disasm(&q->inst, 1);
|
|
||||||
fprintf(stderr, "\n");
|
|
||||||
}
|
|
||||||
fprintf(stderr, "\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Wrap each instruction in a scheduler structure. */
|
/* Wrap each instruction in a scheduler structure. */
|
||||||
uint32_t next_uniform = 0;
|
uint32_t next_sched_uniform = *next_uniform;
|
||||||
while (!list_empty(&c->qpu_inst_list)) {
|
while (!list_empty(&block->qpu_inst_list)) {
|
||||||
struct queued_qpu_inst *inst =
|
struct queued_qpu_inst *inst =
|
||||||
(struct queued_qpu_inst *)c->qpu_inst_list.next;
|
(struct queued_qpu_inst *)block->qpu_inst_list.next;
|
||||||
struct schedule_node *n = rzalloc(mem_ctx, struct schedule_node);
|
struct schedule_node *n = rzalloc(mem_ctx, struct schedule_node);
|
||||||
|
|
||||||
n->inst = inst;
|
n->inst = inst;
|
||||||
|
|
||||||
if (reads_uniform(inst->inst)) {
|
if (reads_uniform(inst->inst)) {
|
||||||
n->uniform = next_uniform++;
|
n->uniform = next_sched_uniform++;
|
||||||
} else {
|
} else {
|
||||||
n->uniform = -1;
|
n->uniform = -1;
|
||||||
}
|
}
|
||||||
list_del(&inst->link);
|
list_del(&inst->link);
|
||||||
list_addtail(&n->link, &schedule_list);
|
list_addtail(&n->link, &schedule_list);
|
||||||
}
|
}
|
||||||
assert(next_uniform == c->num_uniforms);
|
|
||||||
|
|
||||||
calculate_forward_deps(c, &schedule_list);
|
calculate_forward_deps(c, &schedule_list);
|
||||||
calculate_reverse_deps(c, &schedule_list);
|
calculate_reverse_deps(c, &schedule_list);
|
||||||
|
@ -889,7 +871,52 @@ qpu_schedule_instructions(struct vc4_compile *c)
|
||||||
compute_delay(n);
|
compute_delay(n);
|
||||||
}
|
}
|
||||||
|
|
||||||
uint32_t cycles = schedule_instructions(c, &schedule_list);
|
uint32_t cycles = schedule_instructions(c, &schedule_list,
|
||||||
|
orig_uniform_contents,
|
||||||
|
orig_uniform_data,
|
||||||
|
next_uniform);
|
||||||
|
|
||||||
|
ralloc_free(mem_ctx);
|
||||||
|
|
||||||
|
return cycles;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t
|
||||||
|
qpu_schedule_instructions(struct vc4_compile *c)
|
||||||
|
{
|
||||||
|
/* We reorder the uniforms as we schedule instructions, so save the
|
||||||
|
* old data off and replace it.
|
||||||
|
*/
|
||||||
|
uint32_t *uniform_data = c->uniform_data;
|
||||||
|
enum quniform_contents *uniform_contents = c->uniform_contents;
|
||||||
|
c->uniform_contents = ralloc_array(c, enum quniform_contents,
|
||||||
|
c->num_uniforms);
|
||||||
|
c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
|
||||||
|
c->uniform_array_size = c->num_uniforms;
|
||||||
|
uint32_t next_uniform = 0;
|
||||||
|
|
||||||
|
if (debug) {
|
||||||
|
fprintf(stderr, "Pre-schedule instructions\n");
|
||||||
|
qir_for_each_block(block, c) {
|
||||||
|
fprintf(stderr, "BLOCK %d\n", block->index);
|
||||||
|
list_for_each_entry(struct queued_qpu_inst, q,
|
||||||
|
&block->qpu_inst_list, link) {
|
||||||
|
vc4_qpu_disasm(&q->inst, 1);
|
||||||
|
fprintf(stderr, "\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
fprintf(stderr, "\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t cycles = 0;
|
||||||
|
qir_for_each_block(block, c) {
|
||||||
|
cycles += qpu_schedule_instructions_block(c, block,
|
||||||
|
uniform_contents,
|
||||||
|
uniform_data,
|
||||||
|
&next_uniform);
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(next_uniform == c->num_uniforms);
|
||||||
|
|
||||||
if (debug) {
|
if (debug) {
|
||||||
fprintf(stderr, "Post-schedule instructions\n");
|
fprintf(stderr, "Post-schedule instructions\n");
|
||||||
|
@ -897,7 +924,5 @@ qpu_schedule_instructions(struct vc4_compile *c)
|
||||||
fprintf(stderr, "\n");
|
fprintf(stderr, "\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
ralloc_free(mem_ctx);
|
|
||||||
|
|
||||||
return cycles;
|
return cycles;
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue