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radeonsi: fix the top-of-pipe fence on SI 

SI doesn't have MEM.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Marek Olšák 2019-01-17 14:45:10 -05:00
parent e402961e1d
commit a545415eb9
1 changed files with 2 additions and 1 deletions
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3
src/gallium/drivers/radeonsi/si_fence.c
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@ -266,7 +266,8 @@ static void si_fine_fence_set(struct si_context *ctx,
if (flags & PIPE_FLUSH_TOP_OF_PIPE) {
struct radeon_cmdbuf *cs = ctx->gfx_cs;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
radeon_emit(cs, S_370_DST_SEL(ctx->chip_class >= CIK ? V_370_MEM
: V_370_MEM_GRBM) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
radeon_emit(cs, fence_va);