i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
The hardware applies the same channel enable signals to both halves of the compressed instruction which will be just wrong under non-uniform control flow. Fix this by splitting those instructions to SIMD4. Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
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@ -4598,6 +4598,15 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
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*/
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*/
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if (channels_per_grf != (exec_type_size == 8 ? 4 : 8))
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if (channels_per_grf != (exec_type_size == 8 ? 4 : 8))
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max_width = MIN2(max_width, channels_per_grf);
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max_width = MIN2(max_width, channels_per_grf);
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/* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
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* because HW applies the same channel enable signals to both halves of
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* the compressed instruction which will be just wrong under
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* non-uniform control flow.
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*/
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if (devinfo->gen == 7 && !devinfo->is_haswell &&
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(exec_type_size == 8 || type_sz(inst->dst.type) == 8))
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max_width = MIN2(max_width, 4);
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}
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}
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/* Only power-of-two execution sizes are representable in the instruction
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/* Only power-of-two execution sizes are representable in the instruction
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