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i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT 

The hardware applies the same channel enable signals to both halves of
the compressed instruction which will be just wrong under non-uniform
control flow. Fix this by splitting those instructions to SIMD4.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Samuel Iglesias Gonsálvez 2016-08-25 16:05:24 +02:00 committed by Francisco Jerez
parent ebfb703d44
commit a5399e8b1c
1 changed files with 9 additions and 0 deletions
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9
src/intel/compiler/brw_fs.cpp
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@ -4598,6 +4598,15 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
*/
if (channels_per_grf != (exec_type_size == 8 ? 4 : 8))
max_width = MIN2(max_width, channels_per_grf);
/* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
* because HW applies the same channel enable signals to both halves of
* the compressed instruction which will be just wrong under
* non-uniform control flow.
*/
if (devinfo->gen == 7 && !devinfo->is_haswell &&
(exec_type_size == 8 || type_sz(inst->dst.type) == 8))
max_width = MIN2(max_width, 4);
}
/* Only power-of-two execution sizes are representable in the instruction