aco: form sparse load clauses
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7775>
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@ -5887,6 +5887,11 @@ Operand emit_tfe_init(Builder& bld, Temp dst)
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for (unsigned i = 0; i < dst.size(); i++)
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vec->operands[i] = Operand(0u);
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vec->definitions[0] = Definition(tmp);
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/* Since this is fixed to an instruction's definition register, any CSE will
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* just create copies. Copying costs about the same as zero-initialization,
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* but these copies can break up clauses.
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*/
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vec->definitions[0].setNoCSE(true);
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bld.insert(std::move(vec));
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return Operand(tmp);
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@ -851,7 +851,7 @@ class Definition final
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{
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public:
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constexpr Definition() : temp(Temp(0, s1)), reg_(0), isFixed_(0), hasHint_(0),
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isKill_(0), isPrecise_(0), isNUW_(0) {}
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isKill_(0), isPrecise_(0), isNUW_(0), isNoCSE_(0) {}
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Definition(uint32_t index, RegClass type) noexcept
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: temp(index, type) {}
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explicit Definition(Temp tmp) noexcept
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@ -959,6 +959,16 @@ public:
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return isNUW_;
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}
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constexpr void setNoCSE(bool noCSE) noexcept
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{
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isNoCSE_ = noCSE;
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}
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constexpr bool isNoCSE() const noexcept
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{
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return isNoCSE_;
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}
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private:
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Temp temp = Temp(0, s1);
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PhysReg reg_;
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@ -969,6 +979,7 @@ private:
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uint8_t isKill_:1;
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uint8_t isPrecise_:1;
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uint8_t isNUW_:1;
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uint8_t isNoCSE_:1;
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};
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/* can't initialize bit-fields in c++11, so work around using a union */
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uint8_t control_ = 0;
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@ -383,7 +383,7 @@ void process_block(vn_ctx& ctx, Block& block)
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instr->opcode == aco_opcode::p_demote_to_helper)
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ctx.exec_id++;
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if (instr->definitions.empty() || instr->opcode == aco_opcode::p_phi || instr->opcode == aco_opcode::p_linear_phi) {
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if (instr->definitions.empty() || is_phi(instr) || instr->definitions[0].isNoCSE()) {
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new_instructions.emplace_back(std::move(instr));
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continue;
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}
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@ -192,6 +192,8 @@ static void print_definition(const Definition *definition, FILE *output)
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fprintf(output, "(precise)");
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if (definition->isNUW())
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fprintf(output, "(nuw)");
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if (definition->isNoCSE())
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fprintf(output, "(noCSE)");
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fprintf(output, "%%%d", definition->tempId());
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if (definition->isFixed())
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@ -133,3 +133,44 @@ BEGIN_TEST(isel.gs.no_verts)
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fprintf(output, "success\n");
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}
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END_TEST
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BEGIN_TEST(isel.sparse.clause)
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for (unsigned i = GFX10; i <= GFX10; i++) {
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if (!set_variant((chip_class)i))
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continue;
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QoShaderModuleCreateInfo cs = qoShaderModuleCreateInfoGLSL(COMPUTE,
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QO_EXTENSION GL_ARB_sparse_texture2 : require
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layout(local_size_x=1) in;
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layout(binding=0) uniform sampler2D tex;
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layout(binding=0) buffer Buf {
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vec4 res[4];
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uint code[4];
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};
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void main() {
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//>> v5: (noCSE)%zero0 = p_create_vector 0, 0, 0, 0, 0
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//>> v5: %_ = image_sample_lz_o %_, %_, %_, %zero0 dmask:xyzw 2d tfe storage: semantics: scope:invocation
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//>> v5: (noCSE)%zero1 = p_create_vector 0, 0, 0, 0, 0
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//>> v5: %_ = image_sample_lz_o %_, %_, %_, %zero1 dmask:xyzw 2d tfe storage: semantics: scope:invocation
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//>> v5: (noCSE)%zero2 = p_create_vector 0, 0, 0, 0, 0
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//>> v5: %_ = image_sample_lz_o %_, %_, %_, %zero2 dmask:xyzw 2d tfe storage: semantics: scope:invocation
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//>> v5: (noCSE)%zero3 = p_create_vector 0, 0, 0, 0, 0
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//>> v5: %_ = image_sample_lz_o %_, %_, %_, %zero3 dmask:xyzw 2d tfe storage: semantics: scope:invocation
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//>> s_clause 0x3
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//! image_sample_lz_o v#_, v[#_:#_], @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D tfe
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//! image_sample_lz_o v#_, v[#_:#_], @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D tfe
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//! image_sample_lz_o v#_, v[#_:#_], @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D tfe
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//! image_sample_lz_o v#_, v[#_:#_], @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D tfe
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code[0] = sparseTextureOffsetARB(tex, vec2(0.5), ivec2(1, 0), res[0]);
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code[1] = sparseTextureOffsetARB(tex, vec2(0.5), ivec2(2, 0), res[1]);
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code[2] = sparseTextureOffsetARB(tex, vec2(0.5), ivec2(3, 0), res[2]);
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code[3] = sparseTextureOffsetARB(tex, vec2(0.5), ivec2(4, 0), res[3]);
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}
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);
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PipelineBuilder pbld(get_vk_device((chip_class)i));
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pbld.add_cs(cs);
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pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "ACO IR", true);
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pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "Assembly", true);
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}
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END_TEST
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