diff --git a/src/gallium/drivers/iris/iris_blit.c b/src/gallium/drivers/iris/iris_blit.c index 62179edd9bb..4edec91fb08 100644 --- a/src/gallium/drivers/iris/iris_blit.c +++ b/src/gallium/drivers/iris/iris_blit.c @@ -230,6 +230,7 @@ apply_blit_scissor(const struct pipe_scissor_state *scissor, void iris_blorp_surf_for_resource(struct iris_vtable *vtbl, + struct isl_device *isl_dev, struct blorp_surf *surf, struct pipe_resource *p_res, enum isl_aux_usage aux_usage, @@ -250,7 +251,7 @@ iris_blorp_surf_for_resource(struct iris_vtable *vtbl, .buffer = res->bo, .offset = res->offset, .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0, - .mocs = vtbl->mocs(res->bo), + .mocs = vtbl->mocs(res->bo, isl_dev), }, .aux_usage = aux_usage, }; @@ -261,7 +262,7 @@ iris_blorp_surf_for_resource(struct iris_vtable *vtbl, .buffer = res->aux.bo, .offset = res->aux.offset, .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0, - .mocs = vtbl->mocs(res->bo), + .mocs = vtbl->mocs(res->bo, isl_dev), }; surf->clear_color = iris_resource_get_clear_color(res, NULL, NULL); @@ -269,7 +270,7 @@ iris_blorp_surf_for_resource(struct iris_vtable *vtbl, .buffer = res->aux.clear_color_bo, .offset = res->aux.clear_color_offset, .reloc_flags = 0, - .mocs = vtbl->mocs(res->aux.clear_color_bo), + .mocs = vtbl->mocs(res->aux.clear_color_bo, isl_dev), }; } @@ -373,10 +374,12 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE; struct blorp_surf src_surf, dst_surf; - iris_blorp_surf_for_resource(&ice->vtbl, &src_surf, info->src.resource, - src_aux_usage, info->src.level, false); - iris_blorp_surf_for_resource(&ice->vtbl, &dst_surf, info->dst.resource, - dst_aux_usage, info->dst.level, true); + iris_blorp_surf_for_resource(&ice->vtbl, &screen->isl_dev, &src_surf, + info->src.resource, src_aux_usage, + info->src.level, false); + iris_blorp_surf_for_resource(&ice->vtbl, &screen->isl_dev, &dst_surf, + info->dst.resource, dst_aux_usage, + info->dst.level, true); iris_resource_prepare_access(ice, batch, dst_res, info->dst.level, 1, info->dst.box.z, info->dst.box.depth, @@ -523,10 +526,12 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) iris_resource_prepare_access(ice, batch, stc_dst, info->dst.level, 1, info->dst.box.z, info->dst.box.depth, stc_dst_aux_usage, false); - iris_blorp_surf_for_resource(&ice->vtbl, &src_surf, &src_res->base, - stc_src_aux_usage, info->src.level, false); - iris_blorp_surf_for_resource(&ice->vtbl, &dst_surf, &stc_dst->base, - stc_dst_aux_usage, info->dst.level, true); + iris_blorp_surf_for_resource(&ice->vtbl, &screen->isl_dev, &src_surf, + &src_res->base, stc_src_aux_usage, + info->src.level, false); + iris_blorp_surf_for_resource(&ice->vtbl, &screen->isl_dev, &dst_surf, + &stc_dst->base, stc_dst_aux_usage, + info->dst.level, true); for (int slice = 0; slice < info->dst.box.depth; slice++) { iris_batch_maybe_flush(batch, 1500); @@ -653,10 +658,10 @@ iris_copy_region(struct blorp_context *blorp, // XXX: what about one surface being a buffer and not the other? struct blorp_surf src_surf, dst_surf; - iris_blorp_surf_for_resource(&ice->vtbl, &src_surf, src, src_aux_usage, - src_level, false); - iris_blorp_surf_for_resource(&ice->vtbl, &dst_surf, dst, dst_aux_usage, - dst_level, true); + iris_blorp_surf_for_resource(&ice->vtbl, &screen->isl_dev, &src_surf, + src, src_aux_usage, src_level, false); + iris_blorp_surf_for_resource(&ice->vtbl, &screen->isl_dev, &dst_surf, + dst, dst_aux_usage, dst_level, true); iris_resource_prepare_access(ice, batch, src_res, src_level, 1, src_box->z, src_box->depth, diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c index 58c219e9af3..71657bb29e9 100644 --- a/src/gallium/drivers/iris/iris_clear.c +++ b/src/gallium/drivers/iris/iris_clear.c @@ -305,8 +305,8 @@ fast_clear_color(struct iris_context *ice, blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags); struct blorp_surf surf; - iris_blorp_surf_for_resource(&ice->vtbl, &surf, p_res, res->aux.usage, - level, true); + iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev, &surf, + p_res, res->aux.usage, level, true); /* In newer gens (> 9), the hardware will do a linear -> sRGB conversion of * the clear color during the fast clear, if the surface format is of sRGB @@ -375,8 +375,8 @@ clear_color(struct iris_context *ice, box->z, box->depth, aux_usage); struct blorp_surf surf; - iris_blorp_surf_for_resource(&ice->vtbl, &surf, p_res, aux_usage, level, - true); + iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev, &surf, + p_res, aux_usage, level, true); struct blorp_batch blorp_batch; blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags); @@ -583,8 +583,9 @@ clear_depth_stencil(struct iris_context *ice, if (clear_depth && z_res) { iris_resource_prepare_depth(ice, batch, z_res, level, box->z, box->depth); - iris_blorp_surf_for_resource(&ice->vtbl, &z_surf, &z_res->base, - z_res->aux.usage, level, true); + iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev, + &z_surf, &z_res->base, z_res->aux.usage, + level, true); } struct blorp_batch blorp_batch; @@ -594,9 +595,9 @@ clear_depth_stencil(struct iris_context *ice, if (stencil_mask) { iris_resource_prepare_access(ice, batch, stencil_res, level, 1, box->z, box->depth, stencil_res->aux.usage, false); - iris_blorp_surf_for_resource(&ice->vtbl, &stencil_surf, - &stencil_res->base, stencil_res->aux.usage, - level, true); + iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev, + &stencil_surf, &stencil_res->base, + stencil_res->aux.usage, level, true); } blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf, diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index eccb9850da6..b83582658f3 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -498,7 +498,7 @@ struct iris_vtable { struct brw_wm_prog_key *key); void (*populate_cs_key)(const struct iris_context *ice, struct brw_cs_prog_key *key); - uint32_t (*mocs)(const struct iris_bo *bo); + uint32_t (*mocs)(const struct iris_bo *bo, const struct isl_device *isl_dev); void (*lost_genx_state)(struct iris_context *ice, struct iris_batch *batch); }; @@ -776,6 +776,7 @@ void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data, /* iris_blit.c */ void iris_blorp_surf_for_resource(struct iris_vtable *vtbl, + struct isl_device *isl_dev, struct blorp_surf *surf, struct pipe_resource *p_res, enum isl_aux_usage aux_usage, diff --git a/src/gallium/drivers/iris/iris_draw.c b/src/gallium/drivers/iris/iris_draw.c index 9cdf1a2dd0e..497ffc5ccd2 100644 --- a/src/gallium/drivers/iris/iris_draw.c +++ b/src/gallium/drivers/iris/iris_draw.c @@ -326,7 +326,7 @@ iris_update_grid_size_resource(struct iris_context *ice, .size_B = sizeof(grid->grid), .format = ISL_FORMAT_RAW, .stride_B = 1, - .mocs = ice->vtbl.mocs(grid_bo)); + .mocs = ice->vtbl.mocs(grid_bo, isl_dev)); ice->state.dirty |= IRIS_DIRTY_BINDINGS_CS; } diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index 2189825231f..505ededbb59 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -99,7 +99,7 @@ iris_upload_ubo_ssbo_surf_state(struct iris_context *ice, : ISL_FORMAT_R32G32B32A32_FLOAT, .swizzle = ISL_SWIZZLE_IDENTITY, .stride_B = 1, - .mocs = ice->vtbl.mocs(res->bo)); + .mocs = ice->vtbl.mocs(res->bo, &screen->isl_dev)); } static nir_ssa_def * diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index 204d6da7437..752eeef2084 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -480,8 +480,8 @@ iris_resolve_color(struct iris_context *ice, //DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer); struct blorp_surf surf; - iris_blorp_surf_for_resource(&ice->vtbl, &surf, &res->base, res->aux.usage, - level, true); + iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev, &surf, + &res->base, res->aux.usage, level, true); iris_batch_maybe_flush(batch, 1500); @@ -533,8 +533,8 @@ iris_mcs_partial_resolve(struct iris_context *ice, assert(isl_aux_usage_has_mcs(res->aux.usage)); struct blorp_surf surf; - iris_blorp_surf_for_resource(&ice->vtbl, &surf, &res->base, res->aux.usage, - 0, true); + iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev, &surf, + &res->base, res->aux.usage, 0, true); struct blorp_batch blorp_batch; blorp_batch_init(&ice->blorp, &blorp_batch, batch, 0); @@ -684,8 +684,8 @@ iris_hiz_exec(struct iris_context *ice, iris_batch_maybe_flush(batch, 1500); struct blorp_surf surf; - iris_blorp_surf_for_resource(&ice->vtbl, &surf, &res->base, - res->aux.usage, level, true); + iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev, &surf, + &res->base, res->aux.usage, level, true); struct blorp_batch blorp_batch; enum blorp_batch_flags flags = 0; diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index f6f4a7f6168..5a554f4bb1b 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -110,22 +110,10 @@ #include "iris_genx_macros.h" #include "intel/common/gen_guardband.h" -#if GEN_GEN >= 12 -/* TODO: Set PTE to MOCS 61 when the kernel is ready */ -#define MOCS_PTE (3 << 1) -#define MOCS_WB (2 << 1) -#elif GEN_GEN >= 9 -#define MOCS_PTE (1 << 1) -#define MOCS_WB (2 << 1) -#elif GEN_GEN == 8 -#define MOCS_PTE 0x18 -#define MOCS_WB 0x78 -#endif - static uint32_t -mocs(const struct iris_bo *bo) +mocs(const struct iris_bo *bo, const struct isl_device *dev) { - return bo && bo->external ? MOCS_PTE : MOCS_WB; + return bo && bo->external ? dev->mocs.external : dev->mocs.internal; } /** @@ -687,6 +675,7 @@ init_glk_barrier_mode(struct iris_batch *batch, uint32_t value) static void init_state_base_address(struct iris_batch *batch) { + uint32_t mocs = batch->screen->isl_dev.mocs.internal; flush_before_state_base_change(batch); /* We program most base addresses once at context initialization time. @@ -697,12 +686,12 @@ init_state_base_address(struct iris_batch *batch) * updated occasionally. See iris_binder.c for the details there. */ iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) { - sba.GeneralStateMOCS = MOCS_WB; - sba.StatelessDataPortAccessMOCS = MOCS_WB; - sba.DynamicStateMOCS = MOCS_WB; - sba.IndirectObjectMOCS = MOCS_WB; - sba.InstructionMOCS = MOCS_WB; - sba.SurfaceStateMOCS = MOCS_WB; + sba.GeneralStateMOCS = mocs; + sba.StatelessDataPortAccessMOCS = mocs; + sba.DynamicStateMOCS = mocs; + sba.IndirectObjectMOCS = mocs; + sba.InstructionMOCS = mocs; + sba.SurfaceStateMOCS = mocs; sba.GeneralStateBaseAddressModifyEnable = true; sba.DynamicStateBaseAddressModifyEnable = true; @@ -712,7 +701,7 @@ init_state_base_address(struct iris_batch *batch) sba.DynamicStateBufferSizeModifyEnable = true; #if (GEN_GEN >= 9) sba.BindlessSurfaceStateBaseAddressModifyEnable = true; - sba.BindlessSurfaceStateMOCS = MOCS_WB; + sba.BindlessSurfaceStateMOCS = mocs; #endif sba.IndirectObjectBufferSizeModifyEnable = true; sba.InstructionBuffersizeModifyEnable = true; @@ -2109,7 +2098,7 @@ fill_buffer_surface_state(struct isl_device *isl_dev, .format = format, .swizzle = swizzle, .stride_B = cpp, - .mocs = mocs(res->bo)); + .mocs = mocs(res->bo, isl_dev)); } #define SURFACE_STATE_ALIGNMENT 64 @@ -2212,7 +2201,7 @@ fill_surface_state(struct isl_device *isl_dev, struct isl_surf_fill_state_info f = { .surf = surf, .view = view, - .mocs = mocs(res->bo), + .mocs = mocs(res->bo, isl_dev), .address = res->bo->gtt_offset + res->offset, .x_offset_sa = tile_x_sa, .y_offset_sa = tile_y_sa, @@ -2558,7 +2547,7 @@ iris_create_surface(struct pipe_context *ctx, struct isl_surf_fill_state_info f = { .surf = &isl_surf, .view = view, - .mocs = mocs(res->bo), + .mocs = mocs(res->bo, &screen->isl_dev), .address = res->bo->gtt_offset + offset_B, .x_offset_sa = tile_x_sa, .y_offset_sa = tile_y_sa, @@ -2984,7 +2973,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx, info.depth_surf = &zres->surf; info.depth_address = zres->bo->gtt_offset + zres->offset; - info.mocs = mocs(zres->bo); + info.mocs = mocs(zres->bo, isl_dev); view.format = zres->surf.format; @@ -3002,7 +2991,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx, info.stencil_address = stencil_res->bo->gtt_offset + stencil_res->offset; if (!zres) { view.format = stencil_res->surf.format; - info.mocs = mocs(stencil_res->bo); + info.mocs = mocs(stencil_res->bo, isl_dev); } } } @@ -3236,6 +3225,7 @@ iris_set_vertex_buffers(struct pipe_context *ctx, const struct pipe_vertex_buffer *buffers) { struct iris_context *ice = (struct iris_context *) ctx; + struct iris_screen *screen = (struct iris_screen *)ctx->screen; struct iris_genx_state *genx = ice->state.genx; ice->state.bound_vertex_buffers &= ~u_bit_consecutive64(start_slot, count); @@ -3271,7 +3261,7 @@ iris_set_vertex_buffers(struct pipe_context *ctx, vb.BufferSize = res->bo->size - (int) buffer->buffer_offset; vb.BufferStartingAddress = ro_bo(NULL, res->bo->gtt_offset + (int) buffer->buffer_offset); - vb.MOCS = mocs(res->bo); + vb.MOCS = mocs(res->bo, &screen->isl_dev); } else { vb.NullVertexBuffer = true; } @@ -3487,6 +3477,7 @@ iris_set_stream_output_targets(struct pipe_context *ctx, struct iris_context *ice = (struct iris_context *) ctx; struct iris_genx_state *genx = ice->state.genx; uint32_t *so_buffers = genx->so_buffers; + struct iris_screen *screen = (struct iris_screen *)ctx->screen; const bool active = num_targets > 0; if (ice->state.streamout_active != active) { @@ -3572,7 +3563,7 @@ iris_set_stream_output_targets(struct pipe_context *ctx, sob.SOBufferEnable = true; sob.StreamOffsetWriteEnable = true; sob.StreamOutputBufferOffsetAddressEnable = true; - sob.MOCS = mocs(res->bo); + sob.MOCS = mocs(res->bo, &screen->isl_dev); sob.SurfaceSize = MAX2(tgt->base.buffer_size / 4, 1) - 1; sob.StreamOffset = offset; @@ -4970,6 +4961,8 @@ iris_update_surface_base_address(struct iris_batch *batch, if (batch->last_surface_base_address == binder->bo->gtt_offset) return; + uint32_t mocs = batch->screen->isl_dev.mocs.internal; + flush_before_state_base_change(batch); iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) { @@ -4979,14 +4972,14 @@ iris_update_surface_base_address(struct iris_batch *batch, /* The hardware appears to pay attention to the MOCS fields even * if you don't set the "Address Modify Enable" bit for the base. */ - sba.GeneralStateMOCS = MOCS_WB; - sba.StatelessDataPortAccessMOCS = MOCS_WB; - sba.DynamicStateMOCS = MOCS_WB; - sba.IndirectObjectMOCS = MOCS_WB; - sba.InstructionMOCS = MOCS_WB; - sba.SurfaceStateMOCS = MOCS_WB; + sba.GeneralStateMOCS = mocs; + sba.StatelessDataPortAccessMOCS = mocs; + sba.DynamicStateMOCS = mocs; + sba.IndirectObjectMOCS = mocs; + sba.InstructionMOCS = mocs; + sba.SurfaceStateMOCS = mocs; #if GEN_GEN >= 9 - sba.BindlessSurfaceStateMOCS = MOCS_WB; + sba.BindlessSurfaceStateMOCS = mocs; #endif } @@ -5685,7 +5678,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, vb.BufferStartingAddress = ro_bo(NULL, res->bo->gtt_offset + (int) ice->draw.draw_params.offset); - vb.MOCS = mocs(res->bo); + vb.MOCS = mocs(res->bo, &batch->screen->isl_dev); } dynamic_bound |= 1ull << count; count++; @@ -5707,7 +5700,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, vb.BufferStartingAddress = ro_bo(NULL, res->bo->gtt_offset + (int) ice->draw.derived_draw_params.offset); - vb.MOCS = mocs(res->bo); + vb.MOCS = mocs(res->bo, &batch->screen->isl_dev); } dynamic_bound |= 1ull << count; count++; @@ -5953,7 +5946,7 @@ iris_upload_render_state(struct iris_context *ice, uint32_t ib_packet[GENX(3DSTATE_INDEX_BUFFER_length)]; iris_pack_command(GENX(3DSTATE_INDEX_BUFFER), ib_packet, ib) { ib.IndexFormat = draw->index_size >> 1; - ib.MOCS = mocs(bo); + ib.MOCS = mocs(bo, &batch->screen->isl_dev); ib.BufferSize = bo->size - offset; ib.BufferStartingAddress = ro_bo(NULL, bo->gtt_offset + offset); }