nir: Rewrite lower_regs_to_ssa to use the phi builder
This keeps some of Connor's original code. However, while I was at it, I updated this very old pass to a bit more modern NIR.
This commit is contained in:
Jason Ekstrand
parent
67a70889f6
commit
a4d1eb443e
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@ -26,513 +26,266 @@
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*/
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#include "nir.h"
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#include <stdlib.h>
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#include "nir_builder.h"
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#include "nir_phi_builder.h"
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#include "nir_vla.h"
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/*
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* Implements the classic to-SSA algorithm described by Cytron et. al. in
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* "Efficiently Computing Static Single Assignment Form and the Control
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* Dependence Graph."
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*/
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struct regs_to_ssa_state {
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nir_shader *shader;
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/* inserts a phi node of the form reg = phi(reg, reg, reg, ...) */
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static void
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insert_trivial_phi(nir_register *reg, nir_block *block, void *mem_ctx)
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{
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nir_phi_instr *instr = nir_phi_instr_create(mem_ctx);
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instr->dest.reg.reg = reg;
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struct set_entry *entry;
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set_foreach(block->predecessors, entry) {
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nir_block *pred = (nir_block *) entry->key;
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nir_phi_src *src = ralloc(instr, nir_phi_src);
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src->pred = pred;
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src->src.is_ssa = false;
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src->src.reg.base_offset = 0;
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src->src.reg.indirect = NULL;
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src->src.reg.reg = reg;
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exec_list_push_tail(&instr->srcs, &src->node);
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}
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nir_instr_insert_before_block(block, &instr->instr);
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}
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static void
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insert_phi_nodes(nir_function_impl *impl)
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{
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void *mem_ctx = ralloc_parent(impl);
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unsigned *work = calloc(impl->num_blocks, sizeof(unsigned));
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unsigned *has_already = calloc(impl->num_blocks, sizeof(unsigned));
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/*
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* Since the work flags already prevent us from inserting a node that has
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* ever been inserted into W, we don't need to use a set to represent W.
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* Also, since no block can ever be inserted into W more than once, we know
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* that the maximum size of W is the number of basic blocks in the
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* function. So all we need to handle W is an array and a pointer to the
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* next element to be inserted and the next element to be removed.
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*/
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nir_block **W = malloc(impl->num_blocks * sizeof(nir_block *));
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unsigned w_start, w_end;
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unsigned iter_count = 0;
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nir_index_blocks(impl);
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foreach_list_typed(nir_register, reg, node, &impl->registers) {
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if (reg->num_array_elems != 0)
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continue;
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w_start = w_end = 0;
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iter_count++;
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nir_foreach_def(dest, reg) {
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nir_instr *def = dest->reg.parent_instr;
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if (work[def->block->index] < iter_count)
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W[w_end++] = def->block;
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work[def->block->index] = iter_count;
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}
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while (w_start != w_end) {
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nir_block *cur = W[w_start++];
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struct set_entry *entry;
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set_foreach(cur->dom_frontier, entry) {
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nir_block *next = (nir_block *) entry->key;
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/*
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* If there's more than one return statement, then the end block
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* can be a join point for some definitions. However, there are
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* no instructions in the end block, so nothing would use those
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* phi nodes. Of course, we couldn't place those phi nodes
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* anyways due to the restriction of having no instructions in the
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* end block...
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*/
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if (next == impl->end_block)
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continue;
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if (has_already[next->index] < iter_count) {
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insert_trivial_phi(reg, next, mem_ctx);
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has_already[next->index] = iter_count;
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if (work[next->index] < iter_count) {
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work[next->index] = iter_count;
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W[w_end++] = next;
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}
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}
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}
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}
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}
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free(work);
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free(has_already);
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free(W);
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}
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typedef struct {
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nir_ssa_def **stack;
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int index;
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unsigned num_defs; /** < used to add indices to debug names */
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#ifndef NDEBUG
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unsigned stack_size;
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#endif
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} reg_state;
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typedef struct {
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reg_state *states;
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void *mem_ctx;
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nir_instr *parent_instr;
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nir_if *parent_if;
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nir_function_impl *impl;
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/* map from SSA value -> original register */
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struct hash_table *ssa_map;
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} rewrite_state;
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static nir_ssa_def *get_ssa_src(nir_register *reg, rewrite_state *state)
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{
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unsigned index = reg->index;
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if (state->states[index].index == -1) {
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/*
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* We're using an undefined register, create a new undefined SSA value
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* to preserve the information that this source is undefined
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*/
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nir_ssa_undef_instr *instr =
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nir_ssa_undef_instr_create(state->mem_ctx, reg->num_components,
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reg->bit_size);
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/*
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* We could just insert the undefined instruction before the instruction
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* we're rewriting, but we could be rewriting a phi source in which case
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* we can't do that, so do the next easiest thing - insert it at the
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* beginning of the program. In the end, it doesn't really matter where
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* the undefined instructions are because they're going to be ignored
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* in the backend.
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*/
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nir_instr_insert_before_cf_list(&state->impl->body, &instr->instr);
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return &instr->def;
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}
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return state->states[index].stack[state->states[index].index];
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}
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struct nir_phi_builder_value **values;
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};
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static bool
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rewrite_use(nir_src *src, void *_state)
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rewrite_src(nir_src *src, void *_state)
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{
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rewrite_state *state = (rewrite_state *) _state;
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struct regs_to_ssa_state *state = _state;
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if (src->is_ssa)
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return true;
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unsigned index = src->reg.reg->index;
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if (state->states[index].stack == NULL)
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nir_instr *instr = src->parent_instr;
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nir_register *reg = src->reg.reg;
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struct nir_phi_builder_value *value = state->values[reg->index];
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if (!value)
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return true;
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nir_ssa_def *def = get_ssa_src(src->reg.reg, state);
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if (state->parent_instr)
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nir_instr_rewrite_src(state->parent_instr, src, nir_src_for_ssa(def));
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else
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nir_if_rewrite_condition(state->parent_if, nir_src_for_ssa(def));
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nir_block *block;
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if (instr->type == nir_instr_type_phi) {
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nir_phi_src *phi_src = exec_node_data(nir_phi_src, src, src);
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block = phi_src->pred;
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} else {
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block = instr->block;
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}
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nir_ssa_def *def = nir_phi_builder_value_get_block_def(value, block);
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nir_instr_rewrite_src(instr, src, nir_src_for_ssa(def));
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return true;
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}
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static bool
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rewrite_def_forwards(nir_dest *dest, void *_state)
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static void
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rewrite_if_condition(nir_if *nif, struct regs_to_ssa_state *state)
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{
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rewrite_state *state = (rewrite_state *) _state;
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if (nif->condition.is_ssa)
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return;
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nir_block *block = nir_cf_node_as_block(nir_cf_node_prev(&nif->cf_node));
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nir_register *reg = nif->condition.reg.reg;
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struct nir_phi_builder_value *value = state->values[reg->index];
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if (!value)
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return;
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nir_ssa_def *def = nir_phi_builder_value_get_block_def(value, block);
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nir_if_rewrite_condition(nif, nir_src_for_ssa(def));
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}
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static bool
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rewrite_dest(nir_dest *dest, void *_state)
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{
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struct regs_to_ssa_state *state = _state;
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if (dest->is_ssa)
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return true;
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nir_instr *instr = dest->reg.parent_instr;
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nir_register *reg = dest->reg.reg;
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unsigned index = reg->index;
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if (state->states[index].stack == NULL)
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struct nir_phi_builder_value *value = state->values[reg->index];
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if (!value)
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return true;
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char *name = NULL;
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if (dest->reg.reg->name)
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name = ralloc_asprintf(state->mem_ctx, "%s_%u", dest->reg.reg->name,
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state->states[index].num_defs);
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list_del(&dest->reg.def_link);
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nir_ssa_dest_init(state->parent_instr, dest, reg->num_components,
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reg->bit_size, name);
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ralloc_free(name);
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nir_ssa_dest_init(instr, dest, reg->num_components,
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reg->bit_size, reg->name);
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/* push our SSA destination on the stack */
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state->states[index].index++;
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assert(state->states[index].index < state->states[index].stack_size);
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state->states[index].stack[state->states[index].index] = &dest->ssa;
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state->states[index].num_defs++;
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_mesa_hash_table_insert(state->ssa_map, &dest->ssa, reg);
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nir_phi_builder_value_set_block_def(value, instr->block, &dest->ssa);
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return true;
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}
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static void
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rewrite_alu_instr_forward(nir_alu_instr *instr, rewrite_state *state)
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rewrite_alu_instr(nir_alu_instr *alu, struct regs_to_ssa_state *state)
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{
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state->parent_instr = &instr->instr;
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nir_foreach_src(&alu->instr, rewrite_src, state);
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nir_foreach_src(&instr->instr, rewrite_use, state);
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if (instr->dest.dest.is_ssa)
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if (alu->dest.dest.is_ssa)
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return;
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nir_register *reg = instr->dest.dest.reg.reg;
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unsigned index = reg->index;
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if (state->states[index].stack == NULL)
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nir_register *reg = alu->dest.dest.reg.reg;
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struct nir_phi_builder_value *value = state->values[reg->index];
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if (!value)
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return;
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unsigned write_mask = instr->dest.write_mask;
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if (write_mask != (1 << instr->dest.dest.reg.reg->num_components) - 1) {
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/*
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* Calculate the number of components the final instruction, which for
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* per-component things is the number of output components of the
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* instruction and non-per-component things is the number of enabled
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* channels in the write mask.
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unsigned write_mask = alu->dest.write_mask;
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if (write_mask == (1 << reg->num_components) - 1) {
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/* This is the simple case where the instruction writes all the
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* components. We can handle that the same as any other destination.
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*/
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unsigned num_components;
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if (nir_op_infos[instr->op].output_size == 0) {
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unsigned temp = (write_mask & 0x5) + ((write_mask >> 1) & 0x5);
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num_components = (temp & 0x3) + ((temp >> 2) & 0x3);
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} else {
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num_components = nir_op_infos[instr->op].output_size;
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rewrite_dest(&alu->dest.dest, state);
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return;
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}
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/* Calculate the number of components the final instruction, which for
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* per-component things is the number of output components of the
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* instruction and non-per-component things is the number of enabled
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* channels in the write mask.
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*/
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unsigned num_components;
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unsigned vec_swizzle[4] = { 0, 1, 2, 3 };
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if (nir_op_infos[alu->op].output_size == 0) {
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/* Figure out the swizzle we need on the vecN operation and compute
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* the number of components in the SSA def at the same time.
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*/
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num_components = 0;
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for (unsigned index = 0; index < 4; index++) {
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if (write_mask & (1 << index))
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vec_swizzle[index] = num_components++;
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}
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char *name = NULL;
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if (instr->dest.dest.reg.reg->name)
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name = ralloc_asprintf(state->mem_ctx, "%s_%u",
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reg->name, state->states[index].num_defs);
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/* When we change the output writemask, we need to change
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* the swizzles for per-component inputs too
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*/
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for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
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if (nir_op_infos[alu->op].input_sizes[i] != 0)
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continue;
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instr->dest.write_mask = (1 << num_components) - 1;
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list_del(&instr->dest.dest.reg.def_link);
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nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_components,
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reg->bit_size, name);
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ralloc_free(name);
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if (nir_op_infos[instr->op].output_size == 0) {
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/*
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* When we change the output writemask, we need to change the
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* swizzles for per-component inputs too
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* We keep two indices:
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* 1. The index of the original (non-SSA) component
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* 2. The index of the post-SSA, compacted, component
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*
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* We need to map the swizzle component at index 1 to the swizzle
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* component at index 2. Since index 1 is always larger than
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* index 2, we can do it in a single loop.
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*/
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for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
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if (nir_op_infos[instr->op].input_sizes[i] != 0)
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unsigned ssa_index = 0;
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for (unsigned index = 0; index < 4; index++) {
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if (!((write_mask >> index) & 1))
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continue;
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unsigned new_swizzle[4] = {0, 0, 0, 0};
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/*
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* We keep two indices:
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* 1. The index of the original (non-SSA) component
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* 2. The index of the post-SSA, compacted, component
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*
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* We need to map the swizzle component at index 1 to the swizzle
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* component at index 2.
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*/
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unsigned ssa_index = 0;
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for (unsigned index = 0; index < 4; index++) {
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if (!((write_mask >> index) & 1))
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continue;
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new_swizzle[ssa_index] = instr->src[i].swizzle[index];
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ssa_index++;
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}
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for (unsigned j = 0; j < 4; j++)
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instr->src[i].swizzle[j] = new_swizzle[j];
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alu->src[i].swizzle[ssa_index++] = alu->src[i].swizzle[index];
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}
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assert(ssa_index == num_components);
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}
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nir_op op;
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switch (reg->num_components) {
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case 2: op = nir_op_vec2; break;
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case 3: op = nir_op_vec3; break;
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case 4: op = nir_op_vec4; break;
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default: unreachable("not reached");
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}
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nir_alu_instr *vec = nir_alu_instr_create(state->mem_ctx, op);
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vec->dest.dest.reg.reg = reg;
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vec->dest.write_mask = (1 << reg->num_components) - 1;
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nir_ssa_def *old_src = get_ssa_src(reg, state);
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nir_ssa_def *new_src = &instr->dest.dest.ssa;
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unsigned ssa_index = 0;
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for (unsigned i = 0; i < reg->num_components; i++) {
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vec->src[i].src.is_ssa = true;
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if ((write_mask >> i) & 1) {
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vec->src[i].src.ssa = new_src;
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if (nir_op_infos[instr->op].output_size == 0)
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vec->src[i].swizzle[0] = ssa_index;
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else
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vec->src[i].swizzle[0] = i;
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ssa_index++;
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} else {
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vec->src[i].src.ssa = old_src;
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vec->src[i].swizzle[0] = i;
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}
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}
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nir_instr_insert_after(&instr->instr, &vec->instr);
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state->parent_instr = &vec->instr;
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rewrite_def_forwards(&vec->dest.dest, state);
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} else {
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rewrite_def_forwards(&instr->dest.dest, state);
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num_components = nir_op_infos[alu->op].output_size;
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}
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}
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assert(num_components <= 4);
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static void
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rewrite_phi_instr(nir_phi_instr *instr, rewrite_state *state)
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{
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state->parent_instr = &instr->instr;
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rewrite_def_forwards(&instr->dest, state);
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}
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alu->dest.write_mask = (1 << num_components) - 1;
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list_del(&alu->dest.dest.reg.def_link);
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nir_ssa_dest_init(&alu->instr, &alu->dest.dest, num_components,
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reg->bit_size, reg->name);
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static void
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rewrite_instr_forward(nir_instr *instr, rewrite_state *state)
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{
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if (instr->type == nir_instr_type_alu) {
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rewrite_alu_instr_forward(nir_instr_as_alu(instr), state);
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return;
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nir_op vecN_op;
|
||||
switch (reg->num_components) {
|
||||
case 2: vecN_op = nir_op_vec2; break;
|
||||
case 3: vecN_op = nir_op_vec3; break;
|
||||
case 4: vecN_op = nir_op_vec4; break;
|
||||
default: unreachable("not reached");
|
||||
}
|
||||
|
||||
if (instr->type == nir_instr_type_phi) {
|
||||
rewrite_phi_instr(nir_instr_as_phi(instr), state);
|
||||
return;
|
||||
}
|
||||
nir_alu_instr *vec = nir_alu_instr_create(state->shader, vecN_op);
|
||||
|
||||
state->parent_instr = instr;
|
||||
nir_ssa_def *old_src =
|
||||
nir_phi_builder_value_get_block_def(value, alu->instr.block);
|
||||
nir_ssa_def *new_src = &alu->dest.dest.ssa;
|
||||
|
||||
nir_foreach_src(instr, rewrite_use, state);
|
||||
nir_foreach_dest(instr, rewrite_def_forwards, state);
|
||||
}
|
||||
|
||||
static void
|
||||
rewrite_phi_sources(nir_block *block, nir_block *pred, rewrite_state *state)
|
||||
{
|
||||
nir_foreach_instr(instr, block) {
|
||||
if (instr->type != nir_instr_type_phi)
|
||||
break;
|
||||
|
||||
nir_phi_instr *phi_instr = nir_instr_as_phi(instr);
|
||||
|
||||
state->parent_instr = instr;
|
||||
|
||||
nir_foreach_phi_src(src, phi_instr) {
|
||||
if (src->pred == pred) {
|
||||
rewrite_use(&src->src, state);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static bool
|
||||
rewrite_def_backwards(nir_dest *dest, void *_state)
|
||||
{
|
||||
rewrite_state *state = (rewrite_state *) _state;
|
||||
|
||||
if (!dest->is_ssa)
|
||||
return true;
|
||||
|
||||
struct hash_entry *entry =
|
||||
_mesa_hash_table_search(state->ssa_map, &dest->ssa);
|
||||
|
||||
if (!entry)
|
||||
return true;
|
||||
|
||||
nir_register *reg = (nir_register *) entry->data;
|
||||
unsigned index = reg->index;
|
||||
|
||||
state->states[index].index--;
|
||||
assert(state->states[index].index >= -1);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void
|
||||
rewrite_instr_backwards(nir_instr *instr, rewrite_state *state)
|
||||
{
|
||||
nir_foreach_dest(instr, rewrite_def_backwards, state);
|
||||
}
|
||||
|
||||
static void
|
||||
rewrite_block(nir_block *block, rewrite_state *state)
|
||||
{
|
||||
/* This will skip over any instructions after the current one, which is
|
||||
* what we want because those instructions (vector gather, conditional
|
||||
* select) will already be in SSA form.
|
||||
*/
|
||||
nir_foreach_instr_safe(instr, block) {
|
||||
rewrite_instr_forward(instr, state);
|
||||
}
|
||||
|
||||
if (block != state->impl->end_block &&
|
||||
!nir_cf_node_is_last(&block->cf_node) &&
|
||||
nir_cf_node_next(&block->cf_node)->type == nir_cf_node_if) {
|
||||
nir_if *if_stmt = nir_cf_node_as_if(nir_cf_node_next(&block->cf_node));
|
||||
state->parent_instr = NULL;
|
||||
state->parent_if = if_stmt;
|
||||
rewrite_use(&if_stmt->condition, state);
|
||||
}
|
||||
|
||||
if (block->successors[0])
|
||||
rewrite_phi_sources(block->successors[0], block, state);
|
||||
if (block->successors[1])
|
||||
rewrite_phi_sources(block->successors[1], block, state);
|
||||
|
||||
for (unsigned i = 0; i < block->num_dom_children; i++)
|
||||
rewrite_block(block->dom_children[i], state);
|
||||
|
||||
nir_foreach_instr_reverse(instr, block) {
|
||||
rewrite_instr_backwards(instr, state);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
remove_unused_regs(nir_function_impl *impl, rewrite_state *state)
|
||||
{
|
||||
foreach_list_typed_safe(nir_register, reg, node, &impl->registers) {
|
||||
if (state->states[reg->index].stack != NULL)
|
||||
exec_node_remove(®->node);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
init_rewrite_state(nir_function_impl *impl, rewrite_state *state)
|
||||
{
|
||||
state->impl = impl;
|
||||
state->mem_ctx = ralloc_parent(impl);
|
||||
state->ssa_map = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
|
||||
_mesa_key_pointer_equal);
|
||||
state->states = rzalloc_array(NULL, reg_state, impl->reg_alloc);
|
||||
|
||||
foreach_list_typed(nir_register, reg, node, &impl->registers) {
|
||||
assert(reg->index < impl->reg_alloc);
|
||||
if (reg->num_array_elems > 0) {
|
||||
state->states[reg->index].stack = NULL;
|
||||
for (unsigned i = 0; i < reg->num_components; i++) {
|
||||
if (write_mask & (1 << i)) {
|
||||
vec->src[i].src = nir_src_for_ssa(new_src);
|
||||
vec->src[i].swizzle[0] = vec_swizzle[i];
|
||||
} else {
|
||||
/*
|
||||
* Calculate a conservative estimate of the stack size based on the
|
||||
* number of definitions there are. Note that this function *must* be
|
||||
* called after phi nodes are inserted so we can count phi node
|
||||
* definitions too.
|
||||
*/
|
||||
unsigned stack_size = list_length(®->defs);
|
||||
|
||||
state->states[reg->index].stack = ralloc_array(state->states,
|
||||
nir_ssa_def *,
|
||||
stack_size);
|
||||
#ifndef NDEBUG
|
||||
state->states[reg->index].stack_size = stack_size;
|
||||
#endif
|
||||
state->states[reg->index].index = -1;
|
||||
state->states[reg->index].num_defs = 0;
|
||||
vec->src[i].src = nir_src_for_ssa(old_src);
|
||||
vec->src[i].swizzle[0] = i;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
destroy_rewrite_state(rewrite_state *state)
|
||||
{
|
||||
_mesa_hash_table_destroy(state->ssa_map, NULL);
|
||||
ralloc_free(state->states);
|
||||
nir_ssa_dest_init(&vec->instr, &vec->dest.dest, reg->num_components,
|
||||
reg->bit_size, reg->name);
|
||||
nir_instr_insert(nir_after_instr(&alu->instr), &vec->instr);
|
||||
|
||||
nir_phi_builder_value_set_block_def(value, alu->instr.block,
|
||||
&vec->dest.dest.ssa);
|
||||
}
|
||||
|
||||
void
|
||||
nir_lower_regs_to_ssa_impl(nir_function_impl *impl)
|
||||
{
|
||||
nir_metadata_require(impl, nir_metadata_dominance);
|
||||
if (exec_list_is_empty(&impl->registers))
|
||||
return;
|
||||
|
||||
insert_phi_nodes(impl);
|
||||
nir_metadata_require(impl, nir_metadata_block_index |
|
||||
nir_metadata_dominance);
|
||||
nir_index_local_regs(impl);
|
||||
|
||||
rewrite_state state;
|
||||
init_rewrite_state(impl, &state);
|
||||
struct regs_to_ssa_state state;
|
||||
state.shader = impl->function->shader;
|
||||
state.values = malloc(impl->reg_alloc * sizeof(*state.values));
|
||||
|
||||
rewrite_block(nir_start_block(impl), &state);
|
||||
struct nir_phi_builder *phi_build = nir_phi_builder_create(impl);
|
||||
|
||||
remove_unused_regs(impl, &state);
|
||||
const unsigned block_set_words = BITSET_WORDS(impl->num_blocks);
|
||||
NIR_VLA(BITSET_WORD, defs, block_set_words);
|
||||
|
||||
nir_foreach_register(reg, &impl->registers) {
|
||||
if (reg->num_array_elems != 0 || reg->is_packed) {
|
||||
/* This pass only really works on "plain" registers. If it's a
|
||||
* packed or array register, just set the value to NULL so that the
|
||||
* rewrite portion of the pass will know to ignore it.
|
||||
*/
|
||||
state.values[reg->index] = NULL;
|
||||
continue;
|
||||
}
|
||||
|
||||
memset(defs, 0, block_set_words * sizeof(*defs));
|
||||
|
||||
nir_foreach_def(dest, reg)
|
||||
BITSET_SET(defs, dest->reg.parent_instr->block->index);
|
||||
|
||||
state.values[reg->index] =
|
||||
nir_phi_builder_add_value(phi_build, reg->num_components,
|
||||
reg->bit_size, defs);
|
||||
}
|
||||
|
||||
nir_foreach_block(block, impl) {
|
||||
nir_foreach_instr(instr, block) {
|
||||
if (instr->type == nir_instr_type_alu) {
|
||||
rewrite_alu_instr(nir_instr_as_alu(instr), &state);
|
||||
} else {
|
||||
nir_foreach_src(instr, rewrite_src, &state);
|
||||
nir_foreach_dest(instr, rewrite_dest, &state);
|
||||
}
|
||||
}
|
||||
|
||||
nir_if *following_if = nir_block_get_following_if(block);
|
||||
if (following_if)
|
||||
rewrite_if_condition(following_if, &state);
|
||||
}
|
||||
|
||||
nir_phi_builder_finish(phi_build);
|
||||
|
||||
nir_foreach_register_safe(reg, &impl->registers) {
|
||||
if (state.values[reg->index]) {
|
||||
assert(list_empty(®->uses));
|
||||
assert(list_empty(®->if_uses));
|
||||
assert(list_empty(®->defs));
|
||||
exec_node_remove(®->node);
|
||||
}
|
||||
}
|
||||
|
||||
free(state.values);
|
||||
|
||||
nir_metadata_preserve(impl, nir_metadata_block_index |
|
||||
nir_metadata_dominance);
|
||||
|
||||
destroy_rewrite_state(&state);
|
||||
}
|
||||
|
||||
void
|
||||
nir_lower_regs_to_ssa(nir_shader *shader)
|
||||
{
|
||||
assert(exec_list_is_empty(&shader->registers));
|
||||
|
||||
nir_foreach_function(function, shader) {
|
||||
if (function->impl)
|
||||
nir_lower_regs_to_ssa_impl(function->impl);
|
||||
|
|
|
|||
Loading…
Reference in New Issue