gallium/radeon: unify checking streamout enable state
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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466aa57185
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@ -1841,8 +1841,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
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ia_switch_on_eop = true;
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}
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if (rctx->b.streamout.streamout_enabled ||
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rctx->b.streamout.prims_gen_query_enabled)
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if (r600_get_strmout_en(&rctx->b))
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partial_vs_wave = true;
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radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
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@ -2018,7 +2017,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
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rctx->b.family == CHIP_RV635) {
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/* if we have gs shader or streamout
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we need to do a wait idle after every draw */
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if (rctx->gs_shader || rctx->b.streamout.streamout_enabled) {
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if (rctx->gs_shader || r600_get_strmout_en(&rctx->b)) {
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radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
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}
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}
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@ -639,6 +639,12 @@ r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
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(struct pipe_resource *)res);
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}
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static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
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{
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return rctx->streamout.streamout_enabled ||
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rctx->streamout.prims_gen_query_enabled;
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}
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static inline unsigned r600_tex_aniso_filter(unsigned filter)
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{
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if (filter <= 1) return 0;
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@ -311,12 +311,6 @@ void r600_emit_streamout_end(struct r600_common_context *rctx)
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* are no buffers bound.
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*/
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static bool r600_get_strmout_en(struct r600_common_context *rctx)
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{
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return rctx->streamout.streamout_enabled ||
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rctx->streamout.prims_gen_query_enabled;
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}
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static void r600_emit_streamout_enable(struct r600_common_context *rctx,
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struct r600_atom *atom)
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{
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@ -892,8 +892,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
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if ((sctx->b.family == CHIP_HAWAII ||
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sctx->b.family == CHIP_TONGA ||
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sctx->b.family == CHIP_FIJI) &&
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(sctx->b.streamout.streamout_enabled ||
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sctx->b.streamout.prims_gen_query_enabled)) {
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r600_get_strmout_en(&sctx->b)) {
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sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
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}
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