From a4a113b5bc8e3248ebcfeac6f9c9ff24e85caadd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 6 Mar 2018 15:03:09 -0500 Subject: [PATCH] winsys/amdgpu: pad compute IBs v2: pad with PKT2 NOPs on SI Reviewed-by: Alex Deucher --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index d9a95c05093..a3feeb93026 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -1528,6 +1528,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs, } break; case RING_GFX: + case RING_COMPUTE: /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */ if (ws->info.gfx_ib_pad_with_type2) { while (rcs->current.cdw & 7) @@ -1536,7 +1537,8 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs, while (rcs->current.cdw & 7) radeon_emit(rcs, 0xffff1000); /* type3 nop packet */ } - ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4; + if (cs->ring_type == RING_GFX) + ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4; break; case RING_UVD: case RING_UVD_ENC: