radeon/llvm: fix fp immediates on SI
I don't know if this is a good idea, but it fixes the problem at hand. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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@ -232,7 +232,7 @@ uint64_t SICodeEmitter::getMachineOpValue(const MachineInstr &MI,
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case MachineOperand::MO_FPImmediate:
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case MachineOperand::MO_FPImmediate:
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// XXX: Not all instructions can use inline literals
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// XXX: Not all instructions can use inline literals
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// XXX: We should make sure this is a 32-bit constant
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// XXX: We should make sure this is a 32-bit constant
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return LITERAL_REG | (MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue() << 32);
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return LITERAL_REG;
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case MachineOperand::MO_MachineBasicBlock:
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case MachineOperand::MO_MachineBasicBlock:
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return (*BBIndexes.find(MI.getParent()->getNumber())).second -
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return (*BBIndexes.find(MI.getParent()->getNumber())).second -
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@ -321,13 +321,26 @@ uint64_t SICodeEmitter::VOPPostEncode(const MachineInstr &MI,
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// Add one to skip over the destination reg operand.
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// Add one to skip over the destination reg operand.
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for (unsigned opIdx = 1; opIdx < numSrcOps + 1; opIdx++) {
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for (unsigned opIdx = 1; opIdx < numSrcOps + 1; opIdx++) {
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if (!MI.getOperand(opIdx).isReg()) {
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const MachineOperand &MO = MI.getOperand(opIdx);
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switch(MO.getType()) {
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case MachineOperand::MO_Register:
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{
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unsigned reg = MI.getOperand(opIdx).getReg();
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if (AMDGPU::VReg_32RegClass.contains(reg)
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|| AMDGPU::VReg_64RegClass.contains(reg)) {
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Value |= (VGPR_BIT(opIdx)) << vgprBitOffset;
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}
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}
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break;
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case MachineOperand::MO_FPImmediate:
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// XXX: Not all instructions can use inline literals
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// XXX: We should make sure this is a 32-bit constant
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Value |= (MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue() << 32);
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continue;
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continue;
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}
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unsigned reg = MI.getOperand(opIdx).getReg();
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default:
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if (AMDGPU::VReg_32RegClass.contains(reg)
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break;
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|| AMDGPU::VReg_64RegClass.contains(reg)) {
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Value |= (VGPR_BIT(opIdx)) << vgprBitOffset;
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}
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}
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}
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}
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return Value;
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return Value;
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