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radeon/llvm: fix fp immediates on SI 

I don't know if this is a good idea, but it
fixes the problem at hand.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
This commit is contained in:
Christian König 2012-08-01 20:46:39 +02:00
parent 250b7fdd26
commit a3c6607be1
1 changed files with 20 additions and 7 deletions
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27
src/gallium/drivers/radeon/SICodeEmitter.cpp
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@ -232,7 +232,7 @@ uint64_t SICodeEmitter::getMachineOpValue(const MachineInstr &MI,
case MachineOperand::MO_FPImmediate:
// XXX: Not all instructions can use inline literals
// XXX: We should make sure this is a 32-bit constant
return LITERAL_REG | (MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue() << 32);
return LITERAL_REG;
case MachineOperand::MO_MachineBasicBlock:
return (*BBIndexes.find(MI.getParent()->getNumber())).second -
@ -321,13 +321,26 @@ uint64_t SICodeEmitter::VOPPostEncode(const MachineInstr &MI,
// Add one to skip over the destination reg operand.
for (unsigned opIdx = 1; opIdx < numSrcOps + 1; opIdx++) {
if (!MI.getOperand(opIdx).isReg()) {
const MachineOperand &MO = MI.getOperand(opIdx);
switch(MO.getType()) {
case MachineOperand::MO_Register:
{
unsigned reg = MI.getOperand(opIdx).getReg();
if (AMDGPU::VReg_32RegClass.contains(reg)
|| AMDGPU::VReg_64RegClass.contains(reg)) {
Value |= (VGPR_BIT(opIdx)) << vgprBitOffset;
}
}
break;
case MachineOperand::MO_FPImmediate:
// XXX: Not all instructions can use inline literals
// XXX: We should make sure this is a 32-bit constant
Value |= (MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue() << 32);
continue;
}
unsigned reg = MI.getOperand(opIdx).getReg();
if (AMDGPU::VReg_32RegClass.contains(reg)
|| AMDGPU::VReg_64RegClass.contains(reg)) {
Value |= (VGPR_BIT(opIdx)) << vgprBitOffset;
default:
break;
}
}
return Value;