From a3a4517f4147a0a7c1b34a4bcd42de45d552df5f Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 20 May 2021 02:03:07 -0700 Subject: [PATCH] isl: Work around NVIDIA and AMD display pitch requirements MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In the case where we're rendering on the Intel GPU, but displaying on an AMD and NVIDIA GPU, we need to follow their pitch requirements for our linear scanout buffers. Based on a patch by Lionel Landwerlin. Closes: #4706 Reviewed-by: Emma Anholt Reviewed-by: Jason Ekstrand Reviewed-by: Marek Olšák Part-of: --- src/intel/isl/isl.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 2cee638e976..232bd95e065 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1466,9 +1466,12 @@ isl_calc_row_pitch_alignment(const struct isl_device *dev, * PRI_STRIDE Stride (p1254): * * "When using linear memory, this must be at least 64 byte aligned." + * + * However, when displaying on NVIDIA and recent AMD GPUs via PRIME, + * we need a larger pitch of 256 bytes. We do that just in case. */ if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT) - alignment = isl_align(alignment, 64); + alignment = isl_align(alignment, 256); return alignment; }