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i965/gen9: Set HALIGN_16 for all aux buffers 

Just like the previous patch, but for the GEN9 constraints.

v2:
bugfix: Gen9 HALIGN was being set for all miptree buffers (Chad). To address
this, move the check to where the gen8 check is, and do the appropriate
conditional there.

v3:
Remove stray whitespace introduced in v2 (Chad)
Rework comment to show AUX_CCS and AUX_MCS specifically. Remove misworded part
about gen7 (Chad).

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> (v1)
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
Reviewed-by: Chad Versace <chad.versace@intel.com>
This commit is contained in:
Ben Widawsky 2015-05-22 15:57:37 -07:00
parent c4aa041a61
commit a2421623db
1 changed files with 19 additions and 3 deletions
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22
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
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@ -489,10 +489,26 @@ intel_miptree_create_layout(struct brw_context *brw,
if (layout_flags & MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD)
mt->array_layout = ALL_SLICES_AT_EACH_LOD;
/* Use HALIGN_16 if MCS is enabled for non-MSRT */
if (brw->gen >= 8 && num_samples < 2 &&
intel_miptree_is_fast_clear_capable(brw, mt))
/*
* Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
* multisampled or have an AUX buffer attached to it.
*
* GEN | MSRT | AUX_CCS_* or AUX_MCS
* -------------------------------------------
* 9 | HALIGN_16 | HALIGN_16
* 8 | HALIGN_ANY | HALIGN_16
* 7 | ? | ?
* 6 | ? | ?
*/
if (intel_miptree_is_fast_clear_capable(brw, mt)) {
if (brw->gen >= 9 || (brw->gen == 8 && num_samples == 1))
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
} else if (brw->gen >= 9 && num_samples > 1) {
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
} else {
/* For now, nothing else has this requirement */
assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
}
brw_miptree_layout(brw, mt, requested, layout_flags);