gallivm: Fix TGSI_OPCODE_ARR's translation.
Like TGSI_OPCODE_ARL, destination should be an integer. This fixes invalid LLVM IR on an internal state tracker (currently Mesa never emits this opcode). In the future consider making ADDR register also a integer-as-float array, like all other register kinds, or simply replace ADDR & ARR/ARL with integer temp and instructions. Reviewed-by: Dave Airlie <airlied@redhat.com>
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@ -102,8 +102,9 @@ arr_emit(
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struct lp_build_tgsi_context * bld_base,
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struct lp_build_emit_data * emit_data)
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{
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emit_data->output[emit_data->chan] = lp_build_emit_llvm_unary(bld_base,
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TGSI_OPCODE_ROUND, emit_data->args[0]);
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LLVMValueRef tmp = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_ROUND, emit_data->args[0]);
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emit_data->output[emit_data->chan] = LLVMBuildFPToSI(bld_base->base.gallivm->builder, tmp,
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bld_base->uint_bld.vec_type, "");
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}
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/* TGSI_OPCODE_CLAMP */
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@ -820,6 +821,16 @@ arl_emit_cpu(
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bld_base->uint_bld.vec_type, "");
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}
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/* TGSI_OPCODE_ARR (CPU Only) */
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static void
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arr_emit_cpu(
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const struct lp_build_tgsi_action * action,
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struct lp_build_tgsi_context * bld_base,
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struct lp_build_emit_data * emit_data)
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{
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emit_data->output[emit_data->chan] = lp_build_iround(&bld_base->base, emit_data->args[0]);
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}
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/* TGSI_OPCODE_CEIL (CPU Only) */
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static void
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ceil_emit_cpu(
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@ -1166,6 +1177,7 @@ lp_set_default_actions_cpu(
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bld_base->op_actions[TGSI_OPCODE_ABS].emit = abs_emit_cpu;
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bld_base->op_actions[TGSI_OPCODE_ADD].emit = add_emit_cpu;
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bld_base->op_actions[TGSI_OPCODE_ARL].emit = arl_emit_cpu;
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bld_base->op_actions[TGSI_OPCODE_ARR].emit = arr_emit_cpu;
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bld_base->op_actions[TGSI_OPCODE_CEIL].emit = ceil_emit_cpu;
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bld_base->op_actions[TGSI_OPCODE_CND].emit = cnd_emit_cpu;
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bld_base->op_actions[TGSI_OPCODE_COS].emit = cos_emit_cpu;
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@ -1027,6 +1027,8 @@ emit_store_chan(
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break;
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case TGSI_FILE_ADDRESS:
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assert(dtype == TGSI_TYPE_SIGNED);
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assert(LLVMTypeOf(value) == bld_base->base.int_vec_type);
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lp_exec_mask_store(&bld->exec_mask, bld_store, pred, value,
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bld->addr[reg->Register.Index][chan_index]);
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break;
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@ -1377,6 +1379,11 @@ lp_emit_declaration_soa(
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break;
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case TGSI_FILE_ADDRESS:
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/* ADDR registers are the only allocated with an integer LLVM IR type,
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* as they are guaranteed to always have integers.
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* XXX: Not sure if this exception is worthwhile (or the whole idea of
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* an ADDR register for that matter).
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*/
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assert(idx < LP_MAX_TGSI_ADDRS);
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for (i = 0; i < TGSI_NUM_CHANNELS; i++)
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bld->addr[idx][i] = lp_build_alloca(gallivm, bld_base->base.int_vec_type, "addr");
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@ -333,6 +333,7 @@ tgsi_opcode_infer_dst_type( uint opcode )
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case TGSI_OPCODE_MOD:
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case TGSI_OPCODE_UARL:
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case TGSI_OPCODE_ARL:
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case TGSI_OPCODE_ARR:
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case TGSI_OPCODE_IABS:
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case TGSI_OPCODE_ISSG:
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return TGSI_TYPE_SIGNED;
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