(Stephane Marchesin, me) Add support for color (framebuffer) tiling to the radeon and r200 driver
This commit is contained in:
parent
7104ce0a0e
commit
a205137423
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@ -568,6 +568,9 @@ void r200PageFlip( const __DRIdrawablePrivate *dPriv )
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rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset
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rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset
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+ rmesa->r200Screen->fbLocation;
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+ rmesa->r200Screen->fbLocation;
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
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if (rmesa->sarea->tiling_enabled) {
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
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}
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}
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}
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@ -109,6 +109,12 @@ void r200GetLock( r200ContextPtr rmesa, GLuint flags )
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rmesa->lastStamp = dPriv->lastStamp;
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rmesa->lastStamp = dPriv->lastStamp;
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}
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}
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R200_STATECHANGE( rmesa, ctx );
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if (rmesa->sarea->tiling_enabled) {
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
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}
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else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~R200_COLOR_TILE_ENABLE;
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if ( sarea->ctx_owner != rmesa->dri.hwContext ) {
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if ( sarea->ctx_owner != rmesa->dri.hwContext ) {
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sarea->ctx_owner = rmesa->dri.hwContext;
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sarea->ctx_owner = rmesa->dri.hwContext;
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}
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}
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@ -210,6 +210,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define R200_RE_HEIGHT_SHIFT 16
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#define R200_RE_HEIGHT_SHIFT 16
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#define R200_RB3D_COLORPITCH 0x1c48
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#define R200_RB3D_COLORPITCH 0x1c48
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#define R200_COLORPITCH_MASK 0x000001ff8
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#define R200_COLORPITCH_MASK 0x000001ff8
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#define R200_COLOR_TILE_ENABLE (1 << 16)
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#define R200_COLOR_MICROTILE_ENABLE (1 << 17)
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#define R200_COLOR_ENDIAN_NO_SWAP (0 << 18)
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#define R200_COLOR_ENDIAN_NO_SWAP (0 << 18)
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#define R200_COLOR_ENDIAN_WORD_SWAP (1 << 18)
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#define R200_COLOR_ENDIAN_WORD_SWAP (1 << 18)
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#define R200_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
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#define R200_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
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@ -342,10 +342,11 @@ r200CreateScreen( __DRIscreenPrivate *sPriv )
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/* Check if kernel module is new enough to support cube maps */
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/* Check if kernel module is new enough to support cube maps */
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screen->drmSupportsCubeMaps = (sPriv->drmMinor >= 7);
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screen->drmSupportsCubeMaps = (sPriv->drmMinor >= 7);
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/* Check if kernel module is new enough to support blend color and
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/* Check if kernel module is new enough to support blend color and
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separate blend functions/equations */
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separate blend functions/equations */
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screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11);
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screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11);
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}
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}
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/* Check if ddx has set up a surface reg to cover depth buffer */
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screen->depthHasSurface = (sPriv->ddxMajor > 4);
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}
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}
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screen->mmio.handle = dri_priv->registerHandle;
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screen->mmio.handle = dri_priv->registerHandle;
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@ -622,17 +623,17 @@ void * __driCreateNewScreen( __DRInativeDisplay *dpy, int scrn, __DRIscreen *psc
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{
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{
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__DRIscreenPrivate *psp;
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__DRIscreenPrivate *psp;
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static const __DRIversion ddx_expected = { 4, 0, 0 };
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static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
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static const __DRIversion dri_expected = { 4, 0, 0 };
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static const __DRIversion dri_expected = { 4, 0, 0 };
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static const __DRIversion drm_expected = { 1, 5, 0 };
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static const __DRIversion drm_expected = { 1, 5, 0 };
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if ( ! driCheckDriDdxDrmVersions2( "R200",
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if ( ! driCheckDriDdxDrmVersions3( "R200",
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dri_version, & dri_expected,
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dri_version, & dri_expected,
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ddx_version, & ddx_expected,
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ddx_version, & ddx_expected,
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drm_version, & drm_expected ) ) {
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drm_version, & drm_expected ) ) {
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return NULL;
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return NULL;
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}
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}
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psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
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psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
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ddx_version, dri_version, drm_version,
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ddx_version, dri_version, drm_version,
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frame_buffer, pSAREA, fd,
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frame_buffer, pSAREA, fd,
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@ -97,6 +97,7 @@ typedef struct {
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GLboolean drmSupportsCubeMaps; /* need radeon kernel module >=1.7 */
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GLboolean drmSupportsCubeMaps; /* need radeon kernel module >=1.7 */
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GLboolean drmSupportsBlendColor; /* need radeon kernel module >= 1.11 */
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GLboolean drmSupportsBlendColor; /* need radeon kernel module >= 1.11 */
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GLboolean depthHasSurface;
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/* Configuration cache with default values for all contexts */
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/* Configuration cache with default values for all contexts */
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driOptionCache optionCache;
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driOptionCache optionCache;
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@ -154,6 +154,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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* manner as the engine. In each case, the linear block address (ba)
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* manner as the engine. In each case, the linear block address (ba)
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* is calculated, and then wired with x and y to produce the final
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* is calculated, and then wired with x and y to produce the final
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* memory address.
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* memory address.
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* The chip will do address translation on its own if the surface registers
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* are set up correctly. It is not quite enough to get it working with hyperz too...
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*/
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*/
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#define BIT(x,b) ((x & (1<<b))>>b)
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#define BIT(x,b) ((x & (1<<b))>>b)
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@ -161,40 +163,50 @@ static GLuint r200_mba_z32( r200ContextPtr rmesa,
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GLint x, GLint y )
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GLint x, GLint y )
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{
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{
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GLuint pitch = rmesa->r200Screen->frontPitch;
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GLuint pitch = rmesa->r200Screen->frontPitch;
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GLuint b = ((y & 0x7FF) >> 4) * ((pitch & 0xFFF) >> 5) + ((x & 0x7FF) >> 5);
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if (rmesa->r200Screen->depthHasSurface) {
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GLuint a =
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return 4*(x + y*pitch);
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(BIT(x,0) << 2) |
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}
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(BIT(y,0) << 3) |
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else {
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(BIT(x,1) << 4) |
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GLuint b = ((y & 0x7FF) >> 4) * ((pitch & 0xFFF) >> 5) + ((x & 0x7FF) >> 5);
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(BIT(y,1) << 5) |
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GLuint a =
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(BIT(x,3) << 6) |
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(BIT(x,0) << 2) |
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(BIT(x,4) << 7) |
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(BIT(y,0) << 3) |
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(BIT(x,2) << 8) |
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(BIT(x,1) << 4) |
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(BIT(y,2) << 9) |
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(BIT(y,1) << 5) |
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(BIT(y,3) << 10) |
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(BIT(x,3) << 6) |
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(((pitch & 0x20) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y,4)))) << 11) |
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(BIT(x,4) << 7) |
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((b >> 1) << 12);
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(BIT(x,2) << 8) |
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return a;
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(BIT(y,2) << 9) |
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(BIT(y,3) << 10) |
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(((pitch & 0x20) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y,4)))) << 11) |
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((b >> 1) << 12);
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return a;
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}
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}
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}
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static GLuint r200_mba_z16( r200ContextPtr rmesa, GLint x, GLint y )
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static GLuint r200_mba_z16( r200ContextPtr rmesa, GLint x, GLint y )
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{
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{
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GLuint pitch = rmesa->r200Screen->frontPitch;
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GLuint pitch = rmesa->r200Screen->frontPitch;
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GLuint b = ((y & 0x7FF) >> 4) * ((pitch & 0xFFF) >> 6) + ((x & 0x7FF) >> 6);
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if (rmesa->r200Screen->depthHasSurface) {
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GLuint a =
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return 2*(x + y*pitch);
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(BIT(x,0) << 1) |
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}
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(BIT(y,0) << 2) |
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else {
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(BIT(x,1) << 3) |
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GLuint b = ((y & 0x7FF) >> 4) * ((pitch & 0xFFF) >> 6) + ((x & 0x7FF) >> 6);
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(BIT(y,1) << 4) |
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GLuint a =
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(BIT(x,2) << 5) |
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(BIT(x,0) << 1) |
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(BIT(x,4) << 6) |
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(BIT(y,0) << 2) |
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(BIT(x,5) << 7) |
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(BIT(x,1) << 3) |
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(BIT(x,3) << 8) |
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(BIT(y,1) << 4) |
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(BIT(y,2) << 9) |
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(BIT(x,2) << 5) |
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(BIT(y,3) << 10) |
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(BIT(x,4) << 6) |
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(((pitch & 0x40) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y,4)))) << 11) |
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(BIT(x,5) << 7) |
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((b >> 1) << 12);
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(BIT(x,3) << 8) |
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return a;
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(BIT(y,2) << 9) |
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(BIT(y,3) << 10) |
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(((pitch & 0x40) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y,4)))) << 11) |
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((b >> 1) << 12);
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return a;
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}
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}
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}
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@ -1818,6 +1818,9 @@ static void r200DrawBuffer( GLcontext *ctx, GLenum mode )
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rmesa->r200Screen->fbLocation)
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rmesa->r200Screen->fbLocation)
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& R200_COLOROFFSET_MASK);
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& R200_COLOROFFSET_MASK);
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
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if (rmesa->sarea->tiling_enabled) {
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
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}
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}
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}
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@ -499,6 +499,10 @@ void r200InitState( r200ContextPtr rmesa )
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
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R200_COLORPITCH_MASK) |
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R200_COLORPITCH_MASK) |
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R200_COLOR_ENDIAN_NO_SWAP);
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R200_COLOR_ENDIAN_NO_SWAP);
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/* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
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if (rmesa->sarea->tiling_enabled) {
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
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}
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rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
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rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
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R200_BFACE_SOLID |
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R200_BFACE_SOLID |
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@ -1011,6 +1011,9 @@ void radeonPageFlip( const __DRIdrawablePrivate *dPriv )
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rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset
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rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset
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+ rmesa->radeonScreen->fbLocation;
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+ rmesa->radeonScreen->fbLocation;
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
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if (rmesa->sarea->tiling_enabled) {
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
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}
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}
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}
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@ -116,6 +116,12 @@ void radeonGetLock( radeonContextPtr rmesa, GLuint flags )
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rmesa->lastStamp = dPriv->lastStamp;
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rmesa->lastStamp = dPriv->lastStamp;
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}
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}
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RADEON_STATECHANGE( rmesa, ctx );
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if (rmesa->sarea->tiling_enabled) {
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
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}
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else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~RADEON_COLOR_TILE_ENABLE;
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if ( sarea->ctx_owner != rmesa->dri.hwContext ) {
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if ( sarea->ctx_owner != rmesa->dri.hwContext ) {
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int i;
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int i;
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sarea->ctx_owner = rmesa->dri.hwContext;
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sarea->ctx_owner = rmesa->dri.hwContext;
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@ -355,6 +355,10 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
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screen->depthOffset = dri_priv->depthOffset;
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screen->depthOffset = dri_priv->depthOffset;
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screen->depthPitch = dri_priv->depthPitch;
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screen->depthPitch = dri_priv->depthPitch;
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/* Check if ddx has set up a surface reg to cover depth buffer */
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screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
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(screen->chipset & RADEON_CHIPSET_TCL));
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screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
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screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
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+ screen->fbLocation;
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+ screen->fbLocation;
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screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
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screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
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@ -538,11 +542,11 @@ void * __driCreateNewScreen( __DRInativeDisplay *dpy, int scrn, __DRIscreen *psc
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{
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{
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__DRIscreenPrivate *psp;
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__DRIscreenPrivate *psp;
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static const __DRIversion ddx_expected = { 4, 0, 0 };
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static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
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static const __DRIversion dri_expected = { 4, 0, 0 };
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static const __DRIversion dri_expected = { 4, 0, 0 };
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static const __DRIversion drm_expected = { 1, 3, 0 };
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static const __DRIversion drm_expected = { 1, 3, 0 };
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if ( ! driCheckDriDdxDrmVersions2( "Radeon",
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if ( ! driCheckDriDdxDrmVersions3( "Radeon",
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dri_version, & dri_expected,
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dri_version, & dri_expected,
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ddx_version, & ddx_expected,
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ddx_version, & ddx_expected,
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drm_version, & drm_expected ) ) {
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drm_version, & drm_expected ) ) {
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@ -96,6 +96,8 @@ typedef struct {
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unsigned int gart_buffer_offset; /* offset in card memory space */
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unsigned int gart_buffer_offset; /* offset in card memory space */
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unsigned int gart_texture_offset; /* offset in card memory space */
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unsigned int gart_texture_offset; /* offset in card memory space */
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GLboolean depthHasSurface;
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/* Configuration cache with default values for all contexts */
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/* Configuration cache with default values for all contexts */
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driOptionCache optionCache;
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driOptionCache optionCache;
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} radeonScreenRec, *radeonScreenPtr;
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} radeonScreenRec, *radeonScreenPtr;
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@ -189,46 +189,58 @@ do { \
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* manner as the engine. In each case, the linear block address (ba)
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* manner as the engine. In each case, the linear block address (ba)
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* is calculated, and then wired with x and y to produce the final
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* is calculated, and then wired with x and y to produce the final
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* memory address.
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* memory address.
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* The chip will do address translation on its own if the surface registers
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* are set up correctly. It is not quite enough to get it working with hyperz too...
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*/
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*/
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static GLuint radeon_mba_z32( radeonContextPtr rmesa,
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static GLuint radeon_mba_z32( radeonContextPtr rmesa,
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GLint x, GLint y )
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GLint x, GLint y )
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{
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{
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GLuint pitch = rmesa->radeonScreen->frontPitch;
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GLuint pitch = rmesa->radeonScreen->frontPitch;
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GLuint ba, address = 0; /* a[0..1] = 0 */
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if (rmesa->radeonScreen->depthHasSurface) {
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return 4*(x + y*pitch);
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}
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else {
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GLuint ba, address = 0; /* a[0..1] = 0 */
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ba = (y / 16) * (pitch / 16) + (x / 16);
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ba = (y / 16) * (pitch / 16) + (x / 16);
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address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
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address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
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address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
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address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
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address |=
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address |=
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(((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
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(((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
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address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
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address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
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address |= (y & 0x8) << 7; /* a[10] = y[3] */
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address |= (y & 0x8) << 7; /* a[10] = y[3] */
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address |=
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address |=
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(((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
|
(((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
|
||||||
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
|
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
|
||||||
|
|
||||||
return address;
|
return address;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static __inline GLuint radeon_mba_z16( radeonContextPtr rmesa, GLint x, GLint y )
|
static __inline GLuint radeon_mba_z16( radeonContextPtr rmesa, GLint x, GLint y )
|
||||||
{
|
{
|
||||||
GLuint pitch = rmesa->radeonScreen->frontPitch;
|
GLuint pitch = rmesa->radeonScreen->frontPitch;
|
||||||
GLuint ba, address = 0; /* a[0] = 0 */
|
if (rmesa->radeonScreen->depthHasSurface) {
|
||||||
|
return 2*(x + y*pitch);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
GLuint ba, address = 0; /* a[0] = 0 */
|
||||||
|
|
||||||
ba = (y / 16) * (pitch / 32) + (x / 32);
|
ba = (y / 16) * (pitch / 32) + (x / 32);
|
||||||
|
|
||||||
address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
|
address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
|
||||||
address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
|
address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
|
||||||
address |= (x & 0x8) << 4; /* a[7] = x[3] */
|
address |= (x & 0x8) << 4; /* a[7] = x[3] */
|
||||||
address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
|
address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
|
||||||
address |= (y & 0x8) << 7; /* a[10] = y[3] */
|
address |= (y & 0x8) << 7; /* a[10] = y[3] */
|
||||||
address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */
|
address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */
|
||||||
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
|
address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
|
||||||
|
|
||||||
return address;
|
return address;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -1686,6 +1686,9 @@ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
|
||||||
rmesa->radeonScreen->fbLocation)
|
rmesa->radeonScreen->fbLocation)
|
||||||
& RADEON_COLOROFFSET_MASK);
|
& RADEON_COLOROFFSET_MASK);
|
||||||
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
|
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
|
||||||
|
if (rmesa->sarea->tiling_enabled) {
|
||||||
|
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void radeonReadBuffer( GLcontext *ctx, GLenum mode )
|
static void radeonReadBuffer( GLcontext *ctx, GLenum mode )
|
||||||
|
|
|
@ -385,6 +385,10 @@ void radeonInitState( radeonContextPtr rmesa )
|
||||||
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
|
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
|
||||||
RADEON_COLORPITCH_MASK) |
|
RADEON_COLORPITCH_MASK) |
|
||||||
RADEON_COLOR_ENDIAN_NO_SWAP);
|
RADEON_COLOR_ENDIAN_NO_SWAP);
|
||||||
|
/* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
|
||||||
|
if (rmesa->sarea->tiling_enabled) {
|
||||||
|
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
|
||||||
|
}
|
||||||
|
|
||||||
rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
|
rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
|
||||||
RADEON_BFACE_SOLID |
|
RADEON_BFACE_SOLID |
|
||||||
|
|
Loading…
Reference in New Issue