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vc4: Simplify the DISCARD_RANGE handling 

It's really just an upgrade to attempting WHOLE_RESOURCE.  Pulling the
logic out caught two bugs in it: We would try to do so on cubemaps (even
though we're only mapping 1 of the 6 slices), and we would break
persistent coherent mappings by trying to reallocate when we shouldn't.
This commit is contained in:
Eric Anholt 2016-09-08 22:40:44 -07:00
parent 21a27ad956
commit a2014c2eb9
1 changed files with 15 additions and 12 deletions
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27
src/gallium/drivers/vc4/vc4_resource.c
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@ -156,9 +156,22 @@ vc4_resource_transfer_map(struct pipe_context *pctx,
enum pipe_format format = prsc->format;
char *buf;
/* Upgrade DISCARD_RANGE to WHOLE_RESOURCE if the whole resource is
* being mapped.
*/
if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
!(prsc->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) &&
prsc->last_level == 0 &&
prsc->width0 == box->width &&
prsc->height0 == box->height &&
prsc->depth0 == box->depth &&
prsc->array_size == 1) {
usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
}
if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
if (vc4_resource_bo_alloc(rsc)) {
/* If it might be bound as one of our vertex buffers,
* make sure we re-emit vertex buffer state.
*/
@ -177,17 +190,7 @@ vc4_resource_transfer_map(struct pipe_context *pctx,
*/
if (vc4_cl_references_bo(pctx, rsc->bo,
usage & PIPE_TRANSFER_WRITE)) {
if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
prsc->last_level == 0 &&
prsc->width0 == box->width &&
prsc->height0 == box->height &&
prsc->depth0 == box->depth &&
vc4_resource_bo_alloc(rsc)) {
if (prsc->bind & PIPE_BIND_VERTEX_BUFFER)
vc4->dirty |= VC4_DIRTY_VTXBUF;
} else {
vc4_flush(pctx);
}
vc4_flush(pctx);
}
}