From a1dca7069bd46074f43658c87d396bff8cd4dffd Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Wed, 28 May 2014 10:44:13 -0700 Subject: [PATCH] i965/gen6: Force ALL_SLICES_AT_EACH_LOD for separate stencil/hiz MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For gen6 we will use the ALL_SLICES_AT_EACH_LOD miptree layout for separate stencil/hiz. This is needed because gen6 hiz and separate stencil only support a single miplevel. When accessing the other LODs, we will program a tile aligned offset for the bo. PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK] to [DevSNB]: "The separate stencil buffer does not support mip mapping, thus the storage for LODs other than LOD 0 is not needed." We still allocate storage for the other stencil mip-levels within a single texture, but each mip-level will use non-mip-array spacing. PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer "[DevSNB]: The hierarchical depth buffer does not support the LOD field, it is assumed by hardware to be zero. A separate hierarachical depth buffer is required for each LOD used, and the corresponding buffer’s state delivered to hardware each time a new depth buffer state with modified LOD is delivered." We allocate storage for the other hiz mip-levels within a single texture, but each mip-level will use non-mip-array spacing. Signed-off-by: Jordan Justen Reviewed-by: Topi Pohjolainen Acked-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 5dcf0cfdd48..84f998e1399 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -379,6 +379,7 @@ intel_miptree_create_layout(struct brw_context *brw, _mesa_get_format_base_format(format) == GL_DEPTH_STENCIL && (brw->must_use_separate_stencil || (brw->has_separate_stencil && brw_is_hiz_depth_format(brw, format)))) { + const bool force_all_slices_at_each_lod = brw->gen == 6; mt->stencil_mt = intel_miptree_create(brw, mt->target, MESA_FORMAT_S_UINT8, @@ -390,7 +391,7 @@ intel_miptree_create_layout(struct brw_context *brw, true, num_samples, INTEL_MIPTREE_TILING_ANY, - false); + force_all_slices_at_each_lod); if (!mt->stencil_mt) { intel_miptree_release(&mt); return NULL; @@ -1407,6 +1408,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw, struct intel_mipmap_tree *mt) { assert(mt->hiz_mt == NULL); + const bool force_all_slices_at_each_lod = brw->gen == 6; mt->hiz_mt = intel_miptree_create(brw, mt->target, mt->format, @@ -1418,7 +1420,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw, true, mt->num_samples, INTEL_MIPTREE_TILING_ANY, - false); + force_all_slices_at_each_lod); if (!mt->hiz_mt) return false;