r600: support vertex_array_bgra
Use vertex program key mechanism and swizzle during vertex fetch - is there a better way?
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@ -108,6 +108,7 @@ typedef struct StreamDesc
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GLint size; //number of data element
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GLenum type; //data element type
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GLsizei stride;
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GLenum format; // GL_RGBA,GLBGRA
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struct radeon_bo *bo;
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GLint bo_offset;
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@ -798,6 +798,7 @@ GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm,
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GLubyte element,
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GLuint _signed,
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GLboolean normalize,
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GLenum format,
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VTX_FETCH_METHOD * pFetchMethod)
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{
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GLuint client_size_inbyte;
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@ -846,10 +847,21 @@ GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm,
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vfetch_instruction_ptr->m_Word0.f.src_sel_x = SQ_SEL_X;
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vfetch_instruction_ptr->m_Word0.f.mega_fetch_count = mega_fetch_count;
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vfetch_instruction_ptr->m_Word1.f.dst_sel_x = (size < 1) ? SQ_SEL_0 : SQ_SEL_X;
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vfetch_instruction_ptr->m_Word1.f.dst_sel_y = (size < 2) ? SQ_SEL_0 : SQ_SEL_Y;
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vfetch_instruction_ptr->m_Word1.f.dst_sel_z = (size < 3) ? SQ_SEL_0 : SQ_SEL_Z;
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vfetch_instruction_ptr->m_Word1.f.dst_sel_w = (size < 4) ? SQ_SEL_1 : SQ_SEL_W;
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if(format == GL_BGRA)
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{
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vfetch_instruction_ptr->m_Word1.f.dst_sel_x = (size < 1) ? SQ_SEL_0 : SQ_SEL_Z;
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vfetch_instruction_ptr->m_Word1.f.dst_sel_y = (size < 2) ? SQ_SEL_0 : SQ_SEL_Y;
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vfetch_instruction_ptr->m_Word1.f.dst_sel_z = (size < 3) ? SQ_SEL_0 : SQ_SEL_X;
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vfetch_instruction_ptr->m_Word1.f.dst_sel_w = (size < 4) ? SQ_SEL_1 : SQ_SEL_W;
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}
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else
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{
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vfetch_instruction_ptr->m_Word1.f.dst_sel_x = (size < 1) ? SQ_SEL_0 : SQ_SEL_X;
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vfetch_instruction_ptr->m_Word1.f.dst_sel_y = (size < 2) ? SQ_SEL_0 : SQ_SEL_Y;
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vfetch_instruction_ptr->m_Word1.f.dst_sel_z = (size < 3) ? SQ_SEL_0 : SQ_SEL_Z;
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vfetch_instruction_ptr->m_Word1.f.dst_sel_w = (size < 4) ? SQ_SEL_1 : SQ_SEL_W;
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}
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vfetch_instruction_ptr->m_Word1.f.use_const_fields = 1;
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vfetch_instruction_ptr->m_Word1.f.data_format = data_format;
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@ -422,6 +422,7 @@ GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm,
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GLubyte element,
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GLuint _signed,
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GLboolean normalize,
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GLenum format,
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VTX_FETCH_METHOD * pFetchMethod);
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GLboolean cleanup_vfetch_instructions(r700_AssemblerBase* pAsm);
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GLuint gethelpr(r700_AssemblerBase* pAsm);
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@ -179,7 +179,8 @@ GLboolean Process_Vertex_Program_Vfetch_Instructions2(
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context->stream_desc[i].size,
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context->stream_desc[i].element,
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context->stream_desc[i]._signed,
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context->stream_desc[i].normalize,
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context->stream_desc[i].normalize,
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context->stream_desc[i].format,
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&vtxFetchMethod);
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}
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@ -308,6 +309,7 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx,
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vp->aos_desc[i].size = context->stream_desc[i].size;
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vp->aos_desc[i].stride = context->stream_desc[i].stride;
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vp->aos_desc[i].type = context->stream_desc[i].type;
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vp->aos_desc[i].format = context->stream_desc[i].format;
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}
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if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
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@ -368,7 +370,8 @@ void r700SelectVertexShader(GLcontext *ctx)
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match = GL_TRUE;
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for(i=0; i<context->nNumActiveAos; i++)
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{
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if (vp->aos_desc[i].size != context->stream_desc[i].size)
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if (vp->aos_desc[i].size != context->stream_desc[i].size ||
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vp->aos_desc[i].format != context->stream_desc[i].format)
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{
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match = GL_FALSE;
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break;
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@ -471,6 +474,7 @@ static void r700TranslateAttrib(GLcontext *ctx, GLuint unLoc, int count, const s
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pStreamDesc->size = input->Size;
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pStreamDesc->dst_loc = context->nNumActiveAos;
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pStreamDesc->element = unLoc;
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pStreamDesc->format = input->Format;
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switch (pStreamDesc->type)
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{ //GetSurfaceFormat
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@ -39,6 +39,7 @@ typedef struct ArrayDesc //TEMP
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GLint size; //number of data element
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GLenum type; //data element type
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GLsizei stride;
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GLenum format; //GL_RGBA or GL_BGRA
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} ArrayDesc;
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struct r700_vertex_program
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