freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
4e974a9cf3
commit
a13a798926
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@ -10,11 +10,11 @@ git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32840 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9009 bytes, from 2014-01-11 16:56:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 12362 bytes, from 2014-01-07 14:47:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 56545 bytes, from 2014-02-26 16:32:11)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32580 bytes, from 2014-05-09 14:56:06)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10186 bytes, from 2014-05-09 14:56:06)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-09 14:56:06)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 57702 bytes, from 2014-05-09 14:56:06)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26293 bytes, from 2014-05-09 14:56:06)
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Copyright (C) 2013-2014 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -10,11 +10,11 @@ git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32840 bytes, from 2014-01-05 14:44:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9009 bytes, from 2014-01-11 16:56:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 12362 bytes, from 2014-01-07 14:47:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 56545 bytes, from 2014-02-26 16:32:11)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32580 bytes, from 2014-05-09 14:56:06)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10186 bytes, from 2014-05-09 14:56:06)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-09 14:56:06)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 57702 bytes, from 2014-05-09 14:56:06)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26293 bytes, from 2014-05-09 14:56:06)
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Copyright (C) 2013-2014 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -41,31 +41,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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enum a3xx_render_mode {
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RB_RENDERING_PASS = 0,
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RB_TILING_PASS = 1,
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RB_RESOLVE_PASS = 2,
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};
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enum a3xx_tile_mode {
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LINEAR = 0,
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TILE_32X32 = 2,
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};
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enum a3xx_threadmode {
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MULTI = 0,
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SINGLE = 1,
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};
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enum a3xx_instrbuffermode {
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BUFFER = 1,
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};
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enum a3xx_threadsize {
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TWO_QUADS = 0,
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FOUR_QUADS = 1,
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};
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enum a3xx_state_block_id {
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HLSQ_BLOCK_ID_TP_TEX = 2,
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HLSQ_BLOCK_ID_TP_MIPMAP = 3,
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@ -180,12 +160,6 @@ enum a3xx_color_swap {
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XYZW = 3,
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};
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enum a3xx_msaa_samples {
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MSAA_ONE = 0,
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MSAA_TWO = 1,
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MSAA_FOUR = 2,
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};
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enum a3xx_sp_perfcounter_select {
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SP_FS_CFLOW_INSTRUCTIONS = 12,
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SP_FS_FULL_ALU_INSTRUCTIONS = 14,
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@ -212,11 +186,6 @@ enum a3xx_rop_code {
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ROP_SET = 15,
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};
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enum adreno_rb_copy_control_mode {
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RB_COPY_RESOLVE = 1,
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RB_COPY_DEPTH_STENCIL = 5,
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};
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enum a3xx_tex_filter {
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A3XX_TEX_NEAREST = 0,
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A3XX_TEX_LINEAR = 1,
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@ -337,6 +306,7 @@ enum a3xx_tex_type {
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#define REG_A3XX_RBBM_INT_0_STATUS 0x00000064
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#define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080
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#define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001
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#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081
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@ -570,6 +540,10 @@ static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460
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#define REG_A3XX_CP_AHB_FAULT 0x0000054d
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#define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22
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#define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23
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#define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040
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#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000
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#define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
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@ -644,8 +618,26 @@ static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val)
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}
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#define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068
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#define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
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#define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
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static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val)
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{
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return ((((uint32_t)(val * 8.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
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}
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#define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
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#define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
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static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val)
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{
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return ((((uint32_t)(val * 8.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
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}
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#define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069
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#define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
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#define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0
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static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val)
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{
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return ((((uint32_t)(val * 8.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK;
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}
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#define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c
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#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff
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@ -992,6 +984,12 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mod
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{
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return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;
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}
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#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
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#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
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static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
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{
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return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
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}
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#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
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#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
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static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
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@ -1034,6 +1032,12 @@ static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
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{
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return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK;
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}
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#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
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#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
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static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
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{
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return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
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}
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#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
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#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
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static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
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@ -1202,6 +1206,8 @@ static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
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}
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#define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110
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#define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001
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#define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
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#define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111
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@ -1366,10 +1372,36 @@ static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
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}
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#define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a
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#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003
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#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0
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static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val)
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{
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return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK;
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}
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#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc
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#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2
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static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val)
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{
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return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK;
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}
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#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000
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#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12
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static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val)
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{
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return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK;
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}
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#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000
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#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22
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static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val)
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{
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return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK;
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}
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#define REG_A3XX_HLSQ_CL_NDRANGE_1_REG 0x0000220b
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static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; }
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#define REG_A3XX_HLSQ_CL_NDRANGE_2_REG 0x0000220c
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static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; }
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static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; }
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#define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211
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@ -1377,7 +1409,9 @@ static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
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#define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214
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#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG 0x00002215
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static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; }
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static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; }
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#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216
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@ -1624,6 +1658,7 @@ static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
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}
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#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
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#define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
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#define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE 0x00800000
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#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000
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#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24
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static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
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@ -1797,6 +1832,7 @@ static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
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}
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#define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
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#define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
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#define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000
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#define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000
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#define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24
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static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val)
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@ -1976,6 +2012,42 @@ static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
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#define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f
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#define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070
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#define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001
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#define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002
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#define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004
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#define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008
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#define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010
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#define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071
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#define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001
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#define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002
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#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004
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#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008
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#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010
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#define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072
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#define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073
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#define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074
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#define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075
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#define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076
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#define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077
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#define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078
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#define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079
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#define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a
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#define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b
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#define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c
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#define REG_A3XX_VSC_BIN_SIZE 0x00000c01
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#define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
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#define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
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@ -2303,6 +2375,7 @@ static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
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{
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return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK;
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}
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#define A3XX_TEX_CONST_0_NOCONVERT 0x20000000
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#define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000
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#define A3XX_TEX_CONST_0_TYPE__SHIFT 30
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static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)
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@ -10,11 +10,11 @@ git clone https://github.com/freedreno/envytools.git
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|||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32840 bytes, from 2014-01-05 14:44:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9009 bytes, from 2014-01-11 16:56:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 12362 bytes, from 2014-01-07 14:47:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 56545 bytes, from 2014-02-26 16:32:11)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32580 bytes, from 2014-05-09 14:56:06)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10186 bytes, from 2014-05-09 14:56:06)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-09 14:56:06)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 57702 bytes, from 2014-05-09 14:56:06)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26293 bytes, from 2014-05-09 14:56:06)
|
||||
|
||||
Copyright (C) 2013-2014 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
@ -116,6 +116,39 @@ enum adreno_rb_depth_format {
|
|||
DEPTHX_24_8 = 1,
|
||||
};
|
||||
|
||||
enum adreno_rb_copy_control_mode {
|
||||
RB_COPY_RESOLVE = 1,
|
||||
RB_COPY_CLEAR = 2,
|
||||
RB_COPY_DEPTH_STENCIL = 5,
|
||||
};
|
||||
|
||||
enum a3xx_render_mode {
|
||||
RB_RENDERING_PASS = 0,
|
||||
RB_TILING_PASS = 1,
|
||||
RB_RESOLVE_PASS = 2,
|
||||
RB_COMPUTE_PASS = 3,
|
||||
};
|
||||
|
||||
enum a3xx_msaa_samples {
|
||||
MSAA_ONE = 0,
|
||||
MSAA_TWO = 1,
|
||||
MSAA_FOUR = 2,
|
||||
};
|
||||
|
||||
enum a3xx_threadmode {
|
||||
MULTI = 0,
|
||||
SINGLE = 1,
|
||||
};
|
||||
|
||||
enum a3xx_instrbuffermode {
|
||||
BUFFER = 1,
|
||||
};
|
||||
|
||||
enum a3xx_threadsize {
|
||||
TWO_QUADS = 0,
|
||||
FOUR_QUADS = 1,
|
||||
};
|
||||
|
||||
#define REG_AXXX_CP_RB_BASE 0x000001c0
|
||||
|
||||
#define REG_AXXX_CP_RB_CNTL 0x000001c1
|
||||
|
|
|
|||
|
|
@ -10,11 +10,11 @@ git clone https://github.com/freedreno/envytools.git
|
|||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32840 bytes, from 2014-01-05 14:44:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9009 bytes, from 2014-01-11 16:56:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 12362 bytes, from 2014-01-07 14:47:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 56545 bytes, from 2014-02-26 16:32:11)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32580 bytes, from 2014-05-09 14:56:06)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10186 bytes, from 2014-05-09 14:56:06)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-09 14:56:06)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 57702 bytes, from 2014-05-09 14:56:06)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26293 bytes, from 2014-05-09 14:56:06)
|
||||
|
||||
Copyright (C) 2013-2014 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
@ -164,6 +164,11 @@ enum adreno_pm4_type3_packets {
|
|||
CP_SET_BIN = 76,
|
||||
CP_TEST_TWO_MEMS = 113,
|
||||
CP_WAIT_FOR_ME = 19,
|
||||
CP_SET_DRAW_STATE = 67,
|
||||
CP_DRAW_INDX_OFFSET = 56,
|
||||
CP_DRAW_INDIRECT = 40,
|
||||
CP_DRAW_INDX_INDIRECT = 41,
|
||||
CP_DRAW_AUTO = 36,
|
||||
IN_IB_PREFETCH_END = 23,
|
||||
IN_SUBBLK_PREFETCH = 31,
|
||||
IN_INSTR_PREFETCH = 32,
|
||||
|
|
@ -351,6 +356,93 @@ static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
|
|||
return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
|
||||
#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
|
||||
#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
|
||||
#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000700
|
||||
#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000800
|
||||
#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 11
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_OFFSET_0_NOT_EOP 0x00001000
|
||||
#define CP_DRAW_INDX_OFFSET_0_SMALL_INDEX 0x00002000
|
||||
#define CP_DRAW_INDX_OFFSET_0_PRE_DRAW_INITIATOR_ENABLE 0x00004000
|
||||
#define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK 0xffff0000
|
||||
#define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT 16
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_0_NUM_INDICES(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
|
||||
|
||||
#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
|
||||
#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
|
||||
#define CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_BASE(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
|
||||
#define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_DRAW_STATE_0 0x00000000
|
||||
#define CP_SET_DRAW_STATE_0_COUNT__MASK 0x0000ffff
|
||||
#define CP_SET_DRAW_STATE_0_COUNT__SHIFT 0
|
||||
static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK;
|
||||
}
|
||||
#define CP_SET_DRAW_STATE_0_DIRTY 0x00010000
|
||||
#define CP_SET_DRAW_STATE_0_DISABLE 0x00020000
|
||||
#define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS 0x00040000
|
||||
#define CP_SET_DRAW_STATE_0_LOAD_IMMED 0x00080000
|
||||
#define CP_SET_DRAW_STATE_0_GROUP_ID__MASK 0x1f000000
|
||||
#define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT 24
|
||||
static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_DRAW_STATE_1 0x00000001
|
||||
#define CP_SET_DRAW_STATE_1_ADDR__MASK 0xffffffff
|
||||
#define CP_SET_DRAW_STATE_1_ADDR__SHIFT 0
|
||||
static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_0 0x00000000
|
||||
|
||||
#define REG_CP_SET_BIN_1 0x00000001
|
||||
|
|
|
|||
Loading…
Reference in New Issue