nv50/ir/tgsi: add support for atomics
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@ -395,6 +395,14 @@ nv50_ir::DataType Instruction::inferSrcType() const
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case TGSI_OPCODE_USNE:
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case TGSI_OPCODE_USHR:
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case TGSI_OPCODE_UCMP:
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case TGSI_OPCODE_ATOMUADD:
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case TGSI_OPCODE_ATOMXCHG:
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case TGSI_OPCODE_ATOMCAS:
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case TGSI_OPCODE_ATOMAND:
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case TGSI_OPCODE_ATOMOR:
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case TGSI_OPCODE_ATOMXOR:
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case TGSI_OPCODE_ATOMUMIN:
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case TGSI_OPCODE_ATOMUMAX:
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return nv50_ir::TYPE_U32;
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case TGSI_OPCODE_I2F:
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case TGSI_OPCODE_IDIV:
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@ -409,6 +417,8 @@ nv50_ir::DataType Instruction::inferSrcType() const
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case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
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case TGSI_OPCODE_MOD:
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case TGSI_OPCODE_UARL:
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case TGSI_OPCODE_ATOMIMIN:
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case TGSI_OPCODE_ATOMIMAX:
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return nv50_ir::TYPE_S32;
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default:
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return nv50_ir::TYPE_F32;
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@ -568,6 +578,17 @@ static nv50_ir::operation translateOpcode(uint opcode)
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NV50_IR_OPCODE_CASE(GATHER4, TXG);
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NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
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NV50_IR_OPCODE_CASE(ATOMUADD, ATOM);
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NV50_IR_OPCODE_CASE(ATOMXCHG, ATOM);
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NV50_IR_OPCODE_CASE(ATOMCAS, ATOM);
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NV50_IR_OPCODE_CASE(ATOMAND, ATOM);
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NV50_IR_OPCODE_CASE(ATOMOR, ATOM);
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NV50_IR_OPCODE_CASE(ATOMXOR, ATOM);
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NV50_IR_OPCODE_CASE(ATOMUMIN, ATOM);
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NV50_IR_OPCODE_CASE(ATOMUMAX, ATOM);
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NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM);
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NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM);
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NV50_IR_OPCODE_CASE(TEX2, TEX);
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NV50_IR_OPCODE_CASE(TXB2, TXB);
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NV50_IR_OPCODE_CASE(TXL2, TXL);
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@ -1115,6 +1136,7 @@ private:
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void handleLOAD(Value *dst0[4]);
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void handleSTORE();
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void handleATOM(Value *dst0[4], DataType, uint16_t subOp);
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Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
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@ -1965,6 +1987,47 @@ Converter::handleSTORE()
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}
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}
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// XXX: These only work on resources with the single-component u32/s32 formats.
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// Therefore the result is replicated. This might not be intended by TGSI, but
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// operating on more than 1 component would produce undefined results because
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// they do not exist.
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void
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Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
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{
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const int r = tgsi.getSrc(0).getIndex(0);
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std::vector<Value *> srcv;
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std::vector<Value *> defv;
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LValue *dst = getScratch();
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getResourceCoords(srcv, r, 1);
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if (isResourceSpecial(r)) {
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assert(r != TGSI_RESOURCE_INPUT);
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Instruction *insn;
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insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
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insn->subOp = subOp;
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if (subOp == NV50_IR_SUBOP_ATOM_CAS)
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insn->setSrc(2, fetchSrc(3, 0));
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insn->setIndirect(0, 0, srcv.at(0));
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} else {
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operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
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TexTarget targ = getResourceTarget(code, r);
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int idx = code->resources[r].slot;
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defv.push_back(dst);
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srcv.push_back(fetchSrc(2, 0));
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if (subOp == NV50_IR_SUBOP_ATOM_CAS)
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srcv.push_back(fetchSrc(3, 0));
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TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
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tex->subOp = subOp;
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tex->tex.mask = 1;
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tex->setType(ty);
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}
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for (int c = 0; c < 4; ++c)
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if (dst0[c])
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dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
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}
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Converter::Subroutine *
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Converter::getSubroutine(unsigned ip)
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{
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@ -2517,6 +2580,32 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
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case TGSI_OPCODE_STORE:
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handleSTORE();
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break;
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case TGSI_OPCODE_ATOMUADD:
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handleATOM(dst0, dstTy, NV50_IR_SUBOP_ATOM_ADD);
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break;
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case TGSI_OPCODE_ATOMXCHG:
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handleATOM(dst0, dstTy, NV50_IR_SUBOP_ATOM_EXCH);
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break;
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case TGSI_OPCODE_ATOMCAS:
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handleATOM(dst0, dstTy, NV50_IR_SUBOP_ATOM_CAS);
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break;
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case TGSI_OPCODE_ATOMAND:
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handleATOM(dst0, dstTy, NV50_IR_SUBOP_ATOM_AND);
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break;
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case TGSI_OPCODE_ATOMOR:
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handleATOM(dst0, dstTy, NV50_IR_SUBOP_ATOM_OR);
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break;
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case TGSI_OPCODE_ATOMXOR:
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handleATOM(dst0, dstTy, NV50_IR_SUBOP_ATOM_XOR);
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break;
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case TGSI_OPCODE_ATOMUMIN:
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case TGSI_OPCODE_ATOMIMIN:
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handleATOM(dst0, dstTy, NV50_IR_SUBOP_ATOM_MIN);
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break;
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case TGSI_OPCODE_ATOMUMAX:
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case TGSI_OPCODE_ATOMIMAX:
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handleATOM(dst0, dstTy, NV50_IR_SUBOP_ATOM_MAX);
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break;
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default:
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ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
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assert(0);
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