i965: Add support for sampling texture buffer objects on gen7+.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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0b3729c987
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@ -328,7 +328,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
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{
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const struct gl_texture_unit *unit = &ctx->Texture.Unit[i];
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if (unit->_ReallyEnabled) {
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if (unit->_ReallyEnabled && unit->_Current->Target != GL_TEXTURE_BUFFER) {
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const struct gl_texture_object *t = unit->_Current;
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const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
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struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, i);
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@ -43,6 +43,10 @@ gen7_update_sampler_state(struct brw_context *brw, int unit,
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struct gl_sampler_object *gl_sampler = _mesa_get_samplerobj(ctx, unit);
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bool using_nearest = false;
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/* These don't use samplers at all. */
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if (texObj->Target == GL_TEXTURE_BUFFER)
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return;
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switch (gl_sampler->MinFilter) {
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case GL_NEAREST:
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sampler->ss0.min_filter = BRW_MAPFILTER_NEAREST;
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@ -28,6 +28,7 @@
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#include "intel_batchbuffer.h"
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#include "intel_tex.h"
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#include "intel_fbo.h"
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#include "intel_buffer_objects.h"
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#include "brw_context.h"
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#include "brw_state.h"
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@ -53,6 +54,62 @@ gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling)
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}
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}
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static void
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gen7_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit)
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{
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struct brw_context *brw = brw_context(ctx);
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struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
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const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
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struct gen7_surface_state *surf;
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struct intel_buffer_object *intel_obj =
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intel_buffer_object(tObj->BufferObject);
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drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
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gl_format format = tObj->_BufferObjectFormat;
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int texel_size = _mesa_get_format_bytes(format);
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surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
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sizeof(*surf), 32, &brw->wm.surf_offset[surf_index]);
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memset(surf, 0, sizeof(*surf));
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surf->ss0.surface_type = BRW_SURFACE_BUFFER;
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surf->ss0.surface_format = brw_format_for_mesa_format(format);
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surf->ss0.render_cache_read_write = 1;
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if (surf->ss0.surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
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_mesa_problem(NULL, "bad format %s for texture buffer\n",
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_mesa_get_format_name(format));
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}
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if (bo) {
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surf->ss1.base_addr = bo->offset; /* reloc */
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/* Emit relocation to surface contents. Section 5.1.1 of the gen4
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* bspec ("Data Cache") says that the data cache does not exist as
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* a separate cache and is just the sampler cache.
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*/
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drm_intel_bo_emit_reloc(brw->intel.batch.bo,
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(brw->wm.surf_offset[surf_index] +
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offsetof(struct gen7_surface_state, ss1)),
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bo, 0,
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I915_GEM_DOMAIN_SAMPLER, 0);
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int w = intel_obj->Base.Size / texel_size;
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surf->ss2.width = w & 0x7f; /* bits 6:0 of size or width */
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surf->ss2.height = (w >> 7) & 0x1fff; /* bits 19:7 of size or width */
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surf->ss3.depth = (w >> 20) & 0x7f; /* bits 26:20 of size or width */
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surf->ss3.pitch = texel_size - 1;
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} else {
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surf->ss1.base_addr = 0;
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surf->ss2.width = 0;
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surf->ss2.height = 0;
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surf->ss3.depth = 0;
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surf->ss3.pitch = 0;
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}
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gen7_set_surface_tiling(surf, I915_TILING_NONE);
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}
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static void
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gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
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{
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@ -66,6 +123,11 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
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struct gen7_surface_state *surf;
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int width, height, depth;
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if (tObj->Target == GL_TEXTURE_BUFFER) {
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gen7_update_buffer_texture_surface(ctx, unit);
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return;
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}
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intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
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surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
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@ -43,6 +43,10 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit)
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struct intel_texture_image *firstImage;
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int width, height, depth;
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/* TBOs require no validation -- they always just point to their BO. */
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if (tObj->Target == GL_TEXTURE_BUFFER)
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return true;
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/* We know/require this is true by now:
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*/
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assert(intelObj->base._BaseComplete);
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