anv: Break SAMPLE_PATTERN and MULTISAMPLE emit into helpers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1887>
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@ -97,6 +97,10 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
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const unsigned entry_size[4],
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enum gen_urb_deref_block_size *deref_block_size);
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void genX(emit_multisample)(struct anv_batch *batch, uint32_t samples);
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void genX(emit_sample_pattern)(struct anv_batch *batch);
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void genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
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struct anv_address dst, struct anv_address src,
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uint32_t size);
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@ -736,8 +736,9 @@ static void
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emit_ms_state(struct anv_graphics_pipeline *pipeline,
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const VkPipelineMultisampleStateCreateInfo *info)
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{
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uint32_t samples = 1;
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uint32_t log2_samples = 0;
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uint32_t samples = info ? info->rasterizationSamples : 1;
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genX(emit_multisample)(&pipeline->base.batch, samples);
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/* From the Vulkan 1.0 spec:
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* If pSampleMask is NULL, it is treated as if the mask has all bits
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@ -751,46 +752,9 @@ emit_ms_state(struct anv_graphics_pipeline *pipeline,
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uint32_t sample_mask = 0xff;
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#endif
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if (info) {
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samples = info->rasterizationSamples;
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log2_samples = __builtin_ffs(samples) - 1;
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}
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if (info && info->pSampleMask)
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sample_mask &= info->pSampleMask[0];
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anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_MULTISAMPLE), ms) {
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ms.NumberofMultisamples = log2_samples;
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ms.PixelLocation = CENTER;
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#if GEN_GEN >= 8
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/* The PRM says that this bit is valid only for DX9:
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*
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* SW can choose to set this bit only for DX9 API. DX10/OGL API's
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* should not have any effect by setting or not setting this bit.
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*/
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ms.PixelPositionOffsetEnable = false;
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#else
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switch (samples) {
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case 1:
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GEN_SAMPLE_POS_1X(ms.Sample);
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break;
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case 2:
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GEN_SAMPLE_POS_2X(ms.Sample);
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break;
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case 4:
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GEN_SAMPLE_POS_4X(ms.Sample);
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break;
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case 8:
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GEN_SAMPLE_POS_8X(ms.Sample);
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break;
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default:
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break;
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}
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#endif
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}
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anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_SAMPLE_MASK), sm) {
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sm.SampleMask = sample_mask;
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}
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@ -156,18 +156,7 @@ genX(init_device_state)(struct anv_device *device)
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#if GEN_GEN >= 8
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anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
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/* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and
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* VkPhysicalDeviceFeatures::standardSampleLocations.
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*/
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anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
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GEN_SAMPLE_POS_1X(sp._1xSample);
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GEN_SAMPLE_POS_2X(sp._2xSample);
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GEN_SAMPLE_POS_4X(sp._4xSample);
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GEN_SAMPLE_POS_8X(sp._8xSample);
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#if GEN_GEN >= 9
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GEN_SAMPLE_POS_16X(sp._16xSample);
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#endif
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}
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genX(emit_sample_pattern)(&batch);
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/* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
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* section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
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@ -320,6 +309,61 @@ genX(init_device_state)(struct anv_device *device)
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return anv_queue_submit_simple_batch(&device->queue, &batch);
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}
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void
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genX(emit_multisample)(struct anv_batch *batch, uint32_t samples)
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{
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anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
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ms.NumberofMultisamples = __builtin_ffs(samples) - 1;
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ms.PixelLocation = CENTER;
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#if GEN_GEN >= 8
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/* The PRM says that this bit is valid only for DX9:
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*
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* SW can choose to set this bit only for DX9 API. DX10/OGL API's
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* should not have any effect by setting or not setting this bit.
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*/
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ms.PixelPositionOffsetEnable = false;
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#else
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switch (samples) {
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case 1:
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GEN_SAMPLE_POS_1X(ms.Sample);
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break;
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case 2:
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GEN_SAMPLE_POS_2X(ms.Sample);
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break;
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case 4:
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GEN_SAMPLE_POS_4X(ms.Sample);
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break;
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case 8:
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GEN_SAMPLE_POS_8X(ms.Sample);
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break;
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default:
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break;
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}
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#endif
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}
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}
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#if GEN_GEN >= 8
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void
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genX(emit_sample_pattern)(struct anv_batch *batch)
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{
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/* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and
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* VkPhysicalDeviceFeatures::standardSampleLocations.
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*/
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anv_batch_emit(batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
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GEN_SAMPLE_POS_1X(sp._1xSample);
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GEN_SAMPLE_POS_2X(sp._2xSample);
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GEN_SAMPLE_POS_4X(sp._4xSample);
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GEN_SAMPLE_POS_8X(sp._8xSample);
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#if GEN_GEN >= 9
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GEN_SAMPLE_POS_16X(sp._16xSample);
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#endif
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}
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}
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#endif
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static uint32_t
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vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable)
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{
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