intel/compiler: Assert that unsupported tg4 offsets were lowered for XeHP
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14142>
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@ -6105,6 +6105,11 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
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if (brw_texture_offset(instr, i, &offset_bits)) {
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header_bits |= offset_bits;
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} else {
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/* On gfx12.5+, if the offsets are not both constant and in the
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* {-8,7} range, nir_lower_tex() will have already lowered the
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* source offset. So we should never reach this point.
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*/
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assert(devinfo->verx10 < 125);
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srcs[TEX_LOGICAL_SRC_TG4_OFFSET] =
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retype(src, BRW_REGISTER_TYPE_D);
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}
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