dzn: Use CreatePipelineState()
This way we can easily extend the logic to support new features, like depth-bounds testing. Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16948>
This commit is contained in:
Boris Brezillon
parent
83c7fab53f
commit
9feda65a83
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@ -38,6 +38,54 @@
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#include "util/u_debug.h"
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#define D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(__type) \
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ALIGN_POT(ALIGN_POT(sizeof(D3D12_PIPELINE_STATE_SUBOBJECT_TYPE), alignof(__type)) + sizeof(__type), alignof(void *))
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#define MAX_GFX_PIPELINE_STATE_STREAM_SIZE \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(ID3D12RootSignature *) + \
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(D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_SHADER_BYTECODE) * 5) + /* VS, PS, DS, HS, GS */ \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_STREAM_OUTPUT_DESC) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_BLEND_DESC) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(UINT) + /* SampleMask */ \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_RASTERIZER_DESC) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_INPUT_LAYOUT_DESC) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_INDEX_BUFFER_STRIP_CUT_VALUE) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_PRIMITIVE_TOPOLOGY_TYPE) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(struct D3D12_RT_FORMAT_ARRAY) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(DXGI_FORMAT) + /* DS format */ \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(DXGI_SAMPLE_DESC) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_NODE_MASK) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_CACHED_PIPELINE_STATE) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_PIPELINE_STATE_FLAGS) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_DEPTH_STENCIL_DESC1) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_VIEW_INSTANCING_DESC)
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#define MAX_COMPUTE_PIPELINE_STATE_STREAM_SIZE \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(ID3D12RootSignature *) + \
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D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_SHADER_BYTECODE)
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#define d3d12_pipeline_state_stream_new_desc(__stream, __pipetype, __id, __type, __desc) \
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__type *__desc; \
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do { \
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struct { \
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D3D12_PIPELINE_STATE_SUBOBJECT_TYPE type; \
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__type desc; \
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} *__wrapper; \
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(__stream)->SizeInBytes = ALIGN_POT((__stream)->SizeInBytes, alignof(void *)); \
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__wrapper = (void *)((uint8_t *)(__stream)->pPipelineStateSubobjectStream + (__stream)->SizeInBytes); \
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(__stream)->SizeInBytes += sizeof(*__wrapper); \
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assert((__stream)->SizeInBytes < MAX_ ## __pipetype ## _PIPELINE_STATE_STREAM_SIZE); \
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__wrapper->type = D3D12_PIPELINE_STATE_SUBOBJECT_TYPE_ ## __id; \
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__desc = &__wrapper->desc; \
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memset(__desc, 0, sizeof(*__desc)); \
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} while (0)
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#define d3d12_gfx_pipeline_state_stream_new_desc(__stream, __id, __type, __desc) \
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d3d12_pipeline_state_stream_new_desc(__stream, GFX, __id, __type, __desc)
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#define d3d12_compute_pipeline_state_stream_new_desc(__stream, __id, __type, __desc) \
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d3d12_pipeline_state_stream_new_desc(__stream, COMPUTE, __id, __type, __desc)
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static dxil_spirv_shader_stage
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to_dxil_shader_stage(VkShaderStageFlagBits in)
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{
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@ -180,15 +228,30 @@ dzn_pipeline_compile_shader(struct dzn_device *device,
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}
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static D3D12_SHADER_BYTECODE *
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dzn_pipeline_get_gfx_shader_slot(D3D12_GRAPHICS_PIPELINE_STATE_DESC *desc,
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dzn_pipeline_get_gfx_shader_slot(D3D12_PIPELINE_STATE_STREAM_DESC *stream,
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gl_shader_stage in)
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{
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switch (in) {
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case MESA_SHADER_VERTEX: return &desc->VS;
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case MESA_SHADER_TESS_CTRL: return &desc->DS;
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case MESA_SHADER_TESS_EVAL: return &desc->HS;
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case MESA_SHADER_GEOMETRY: return &desc->GS;
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case MESA_SHADER_FRAGMENT: return &desc->PS;
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case MESA_SHADER_VERTEX: {
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d3d12_gfx_pipeline_state_stream_new_desc(stream, VS, D3D12_SHADER_BYTECODE, desc);
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return desc;
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}
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case MESA_SHADER_TESS_CTRL: {
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d3d12_gfx_pipeline_state_stream_new_desc(stream, DS, D3D12_SHADER_BYTECODE, desc);
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return desc;
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}
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case MESA_SHADER_TESS_EVAL: {
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d3d12_gfx_pipeline_state_stream_new_desc(stream, HS, D3D12_SHADER_BYTECODE, desc);
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return desc;
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}
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case MESA_SHADER_GEOMETRY: {
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d3d12_gfx_pipeline_state_stream_new_desc(stream, GS, D3D12_SHADER_BYTECODE, desc);
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return desc;
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}
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case MESA_SHADER_FRAGMENT: {
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d3d12_gfx_pipeline_state_stream_new_desc(stream, PS, D3D12_SHADER_BYTECODE, desc);
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return desc;
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}
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default: unreachable("Unsupported stage");
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}
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}
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@ -197,9 +260,10 @@ static VkResult
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dzn_graphics_pipeline_compile_shaders(struct dzn_device *device,
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const struct dzn_graphics_pipeline *pipeline,
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const struct dzn_pipeline_layout *layout,
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D3D12_GRAPHICS_PIPELINE_STATE_DESC *out,
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D3D12_PIPELINE_STATE_STREAM_DESC *out,
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D3D12_INPUT_ELEMENT_DESC *attribs,
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D3D12_INPUT_ELEMENT_DESC *inputs,
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D3D12_SHADER_BYTECODE **shaders,
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const VkGraphicsPipelineCreateInfo *info)
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{
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const VkPipelineViewportStateCreateInfo *vp_info =
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@ -333,8 +397,11 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device,
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var->data.driver_location = drv_loc++;
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}
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out->InputLayout.pInputElementDescs = drv_loc ? inputs : NULL;
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out->InputLayout.NumElements = drv_loc;
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if (drv_loc > 0) {
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d3d12_gfx_pipeline_state_stream_new_desc(out, INPUT_LAYOUT, D3D12_INPUT_LAYOUT_DESC, desc);
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desc->pInputElementDescs = inputs;
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desc->NumElements = drv_loc;
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}
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}
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/* Last step: translate NIR shaders into DXIL modules */
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@ -345,6 +412,8 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device,
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ret = dzn_pipeline_compile_shader(device, stages[stage].nir, slot);
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if (ret != VK_SUCCESS)
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goto out;
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shaders[stage] = slot;
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}
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out:
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@ -466,25 +535,34 @@ to_prim_topology(VkPrimitiveTopology in, unsigned patch_control_points)
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static void
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dzn_graphics_pipeline_translate_ia(struct dzn_graphics_pipeline *pipeline,
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D3D12_GRAPHICS_PIPELINE_STATE_DESC *out,
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D3D12_PIPELINE_STATE_STREAM_DESC *out,
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const VkGraphicsPipelineCreateInfo *in)
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{
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const VkPipelineInputAssemblyStateCreateInfo *in_ia =
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in->pInputAssemblyState;
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bool has_tes = false;
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for (uint32_t i = 0; i < in->stageCount; i++) {
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if (in->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
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in->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
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has_tes = true;
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break;
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}
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}
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const VkPipelineTessellationStateCreateInfo *in_tes =
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(out->DS.pShaderBytecode && out->HS.pShaderBytecode) ?
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in->pTessellationState : NULL;
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has_tes ? in->pTessellationState : NULL;
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out->PrimitiveTopologyType = to_prim_topology_type(in_ia->topology);
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d3d12_gfx_pipeline_state_stream_new_desc(out, PRIMITIVE_TOPOLOGY, D3D12_PRIMITIVE_TOPOLOGY_TYPE, prim_top_type);
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*prim_top_type = to_prim_topology_type(in_ia->topology);
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pipeline->ia.triangle_fan = in_ia->topology == VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN;
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pipeline->ia.topology =
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to_prim_topology(in_ia->topology, in_tes ? in_tes->patchControlPoints : 0);
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/* FIXME: does that work for u16 index buffers? */
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d3d12_gfx_pipeline_state_stream_new_desc(out, IB_STRIP_CUT_VALUE, D3D12_INDEX_BUFFER_STRIP_CUT_VALUE, ib_strip_cut);
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if (in_ia->primitiveRestartEnable)
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out->IBStripCutValue = D3D12_INDEX_BUFFER_STRIP_CUT_VALUE_0xFFFFFFFF;
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*ib_strip_cut = D3D12_INDEX_BUFFER_STRIP_CUT_VALUE_0xFFFFFFFF;
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else
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out->IBStripCutValue = D3D12_INDEX_BUFFER_STRIP_CUT_VALUE_DISABLED;
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*ib_strip_cut = D3D12_INDEX_BUFFER_STRIP_CUT_VALUE_DISABLED;
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}
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static D3D12_FILL_MODE
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@ -512,7 +590,7 @@ translate_cull_mode(VkCullModeFlags in)
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static void
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dzn_graphics_pipeline_translate_rast(struct dzn_graphics_pipeline *pipeline,
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D3D12_GRAPHICS_PIPELINE_STATE_DESC *out,
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D3D12_PIPELINE_STATE_STREAM_DESC *out,
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const VkGraphicsPipelineCreateInfo *in)
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{
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const VkPipelineRasterizationStateCreateInfo *in_rast =
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@ -534,15 +612,16 @@ dzn_graphics_pipeline_translate_rast(struct dzn_graphics_pipeline *pipeline,
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}
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}
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out->RasterizerState.DepthClipEnable = !in_rast->depthClampEnable;
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out->RasterizerState.FillMode = translate_polygon_mode(in_rast->polygonMode);
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out->RasterizerState.CullMode = translate_cull_mode(in_rast->cullMode);
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out->RasterizerState.FrontCounterClockwise =
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d3d12_gfx_pipeline_state_stream_new_desc(out, RASTERIZER, D3D12_RASTERIZER_DESC, desc);
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desc->DepthClipEnable = !in_rast->depthClampEnable;
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desc->FillMode = translate_polygon_mode(in_rast->polygonMode);
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desc->CullMode = translate_cull_mode(in_rast->cullMode);
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desc->FrontCounterClockwise =
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in_rast->frontFace == VK_FRONT_FACE_COUNTER_CLOCKWISE;
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if (in_rast->depthBiasEnable) {
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out->RasterizerState.DepthBias = in_rast->depthBiasConstantFactor;
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out->RasterizerState.SlopeScaledDepthBias = in_rast->depthBiasSlopeFactor;
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out->RasterizerState.DepthBiasClamp = in_rast->depthBiasClamp;
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desc->DepthBias = in_rast->depthBiasConstantFactor;
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desc->SlopeScaledDepthBias = in_rast->depthBiasSlopeFactor;
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desc->DepthBiasClamp = in_rast->depthBiasClamp;
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}
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assert(in_rast->lineWidth == 1.0f);
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@ -550,7 +629,7 @@ dzn_graphics_pipeline_translate_rast(struct dzn_graphics_pipeline *pipeline,
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static void
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dzn_graphics_pipeline_translate_ms(struct dzn_graphics_pipeline *pipeline,
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D3D12_GRAPHICS_PIPELINE_STATE_DESC *out,
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D3D12_PIPELINE_STATE_STREAM_DESC *out,
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const VkGraphicsPipelineCreateInfo *in)
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{
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const VkPipelineRasterizationStateCreateInfo *in_rast =
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@ -558,12 +637,19 @@ dzn_graphics_pipeline_translate_ms(struct dzn_graphics_pipeline *pipeline,
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const VkPipelineMultisampleStateCreateInfo *in_ms =
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in_rast->rasterizerDiscardEnable ? NULL : in->pMultisampleState;
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if (!in_ms)
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return;
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/* TODO: minSampleShading (use VRS), alphaToOneEnable */
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out->SampleDesc.Count = in_ms ? in_ms->rasterizationSamples : 1;
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out->SampleDesc.Quality = 0;
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out->SampleMask = in_ms && in_ms->pSampleMask ?
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*in_ms->pSampleMask :
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(1 << out->SampleDesc.Count) - 1;
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d3d12_gfx_pipeline_state_stream_new_desc(out, SAMPLE_DESC, DXGI_SAMPLE_DESC, desc);
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desc->Count = in_ms ? in_ms->rasterizationSamples : 1;
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desc->Quality = 0;
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if (!in_ms->pSampleMask)
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return;
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d3d12_gfx_pipeline_state_stream_new_desc(out, SAMPLE_MASK, UINT, mask);
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*mask = *in_ms->pSampleMask;
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}
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static D3D12_STENCIL_OP
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@ -584,7 +670,7 @@ translate_stencil_op(VkStencilOp in)
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static void
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translate_stencil_test(struct dzn_graphics_pipeline *pipeline,
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D3D12_GRAPHICS_PIPELINE_STATE_DESC *out,
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D3D12_DEPTH_STENCIL_DESC1 *out,
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const VkGraphicsPipelineCreateInfo *in)
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{
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const VkPipelineDepthStencilStateCreateInfo *in_zsa =
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@ -680,12 +766,12 @@ translate_stencil_test(struct dzn_graphics_pipeline *pipeline,
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* reference. Until we have proper support for independent front/back
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* stencil test, let's prioritize the front setup when both are active.
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*/
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out->DepthStencilState.StencilReadMask =
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out->StencilReadMask =
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front_test_uses_ref ?
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pipeline->zsa.stencil_test.front.compare_mask :
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back_test_uses_ref ?
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pipeline->zsa.stencil_test.back.compare_mask : 0;
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out->DepthStencilState.StencilWriteMask =
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out->StencilWriteMask =
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pipeline->zsa.stencil_test.front.write_mask ?
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pipeline->zsa.stencil_test.front.write_mask :
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pipeline->zsa.stencil_test.back.write_mask;
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@ -695,7 +781,7 @@ translate_stencil_test(struct dzn_graphics_pipeline *pipeline,
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static void
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dzn_graphics_pipeline_translate_zsa(struct dzn_graphics_pipeline *pipeline,
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D3D12_GRAPHICS_PIPELINE_STATE_DESC *out,
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D3D12_PIPELINE_STATE_STREAM_DESC *out,
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const VkGraphicsPipelineCreateInfo *in)
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{
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const VkPipelineRasterizationStateCreateInfo *in_rast =
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@ -707,35 +793,36 @@ dzn_graphics_pipeline_translate_zsa(struct dzn_graphics_pipeline *pipeline,
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return;
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/* TODO: depthBoundsTestEnable */
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d3d12_gfx_pipeline_state_stream_new_desc(out, DEPTH_STENCIL1, D3D12_DEPTH_STENCIL_DESC1, desc);
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out->DepthStencilState.DepthEnable = in_zsa->depthTestEnable;
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out->DepthStencilState.DepthWriteMask =
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desc->DepthEnable = in_zsa->depthTestEnable;
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desc->DepthWriteMask =
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in_zsa->depthWriteEnable ?
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D3D12_DEPTH_WRITE_MASK_ALL : D3D12_DEPTH_WRITE_MASK_ZERO;
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out->DepthStencilState.DepthFunc =
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desc->DepthFunc =
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dzn_translate_compare_op(in_zsa->depthCompareOp);
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out->DepthStencilState.StencilEnable = in_zsa->stencilTestEnable;
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desc->StencilEnable = in_zsa->stencilTestEnable;
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if (in_zsa->stencilTestEnable) {
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out->DepthStencilState.FrontFace.StencilFailOp =
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desc->FrontFace.StencilFailOp =
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translate_stencil_op(in_zsa->front.failOp);
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out->DepthStencilState.FrontFace.StencilDepthFailOp =
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desc->FrontFace.StencilDepthFailOp =
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translate_stencil_op(in_zsa->front.depthFailOp);
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out->DepthStencilState.FrontFace.StencilPassOp =
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desc->FrontFace.StencilPassOp =
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translate_stencil_op(in_zsa->front.passOp);
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out->DepthStencilState.FrontFace.StencilFunc =
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desc->FrontFace.StencilFunc =
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dzn_translate_compare_op(in_zsa->front.compareOp);
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out->DepthStencilState.BackFace.StencilFailOp =
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desc->BackFace.StencilFailOp =
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translate_stencil_op(in_zsa->back.failOp);
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out->DepthStencilState.BackFace.StencilDepthFailOp =
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desc->BackFace.StencilDepthFailOp =
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translate_stencil_op(in_zsa->back.depthFailOp);
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out->DepthStencilState.BackFace.StencilPassOp =
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desc->BackFace.StencilPassOp =
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translate_stencil_op(in_zsa->back.passOp);
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out->DepthStencilState.BackFace.StencilFunc =
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desc->BackFace.StencilFunc =
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dzn_translate_compare_op(in_zsa->back.compareOp);
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pipeline->zsa.stencil_test.enable = true;
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translate_stencil_test(pipeline, out, in);
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translate_stencil_test(pipeline, desc, in);
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}
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}
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@ -814,7 +901,7 @@ translate_logic_op(VkLogicOp in)
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static void
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dzn_graphics_pipeline_translate_blend(struct dzn_graphics_pipeline *pipeline,
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D3D12_GRAPHICS_PIPELINE_STATE_DESC *out,
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D3D12_PIPELINE_STATE_STREAM_DESC *out,
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const VkGraphicsPipelineCreateInfo *in)
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{
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const VkPipelineRasterizationStateCreateInfo *in_rast =
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@ -827,10 +914,11 @@ dzn_graphics_pipeline_translate_blend(struct dzn_graphics_pipeline *pipeline,
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if (!in_blend || !in_ms)
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return;
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d3d12_gfx_pipeline_state_stream_new_desc(out, BLEND, D3D12_BLEND_DESC, desc);
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D3D12_LOGIC_OP logicop =
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in_blend->logicOpEnable ?
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translate_logic_op(in_blend->logicOp) : D3D12_LOGIC_OP_NOOP;
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out->BlendState.AlphaToCoverageEnable = in_ms->alphaToCoverageEnable;
|
||||
desc->AlphaToCoverageEnable = in_ms->alphaToCoverageEnable;
|
||||
memcpy(pipeline->blend.constants, in_blend->blendConstants,
|
||||
sizeof(pipeline->blend.constants));
|
||||
|
||||
|
|
@ -838,29 +926,29 @@ dzn_graphics_pipeline_translate_blend(struct dzn_graphics_pipeline *pipeline,
|
|||
if (i > 0 &&
|
||||
!memcmp(&in_blend->pAttachments[i - 1], &in_blend->pAttachments[i],
|
||||
sizeof(*in_blend->pAttachments)))
|
||||
out->BlendState.IndependentBlendEnable = true;
|
||||
desc->IndependentBlendEnable = true;
|
||||
|
||||
out->BlendState.RenderTarget[i].BlendEnable =
|
||||
desc->RenderTarget[i].BlendEnable =
|
||||
in_blend->pAttachments[i].blendEnable;
|
||||
in_blend->logicOpEnable;
|
||||
out->BlendState.RenderTarget[i].RenderTargetWriteMask =
|
||||
desc->RenderTarget[i].RenderTargetWriteMask =
|
||||
in_blend->pAttachments[i].colorWriteMask;
|
||||
|
||||
if (in_blend->logicOpEnable) {
|
||||
out->BlendState.RenderTarget[i].LogicOpEnable = true;
|
||||
out->BlendState.RenderTarget[i].LogicOp = logicop;
|
||||
desc->RenderTarget[i].LogicOpEnable = true;
|
||||
desc->RenderTarget[i].LogicOp = logicop;
|
||||
} else {
|
||||
out->BlendState.RenderTarget[i].SrcBlend =
|
||||
desc->RenderTarget[i].SrcBlend =
|
||||
translate_blend_factor(in_blend->pAttachments[i].srcColorBlendFactor, false);
|
||||
out->BlendState.RenderTarget[i].DestBlend =
|
||||
desc->RenderTarget[i].DestBlend =
|
||||
translate_blend_factor(in_blend->pAttachments[i].dstColorBlendFactor, false);
|
||||
out->BlendState.RenderTarget[i].BlendOp =
|
||||
desc->RenderTarget[i].BlendOp =
|
||||
translate_blend_op(in_blend->pAttachments[i].colorBlendOp);
|
||||
out->BlendState.RenderTarget[i].SrcBlendAlpha =
|
||||
desc->RenderTarget[i].SrcBlendAlpha =
|
||||
translate_blend_factor(in_blend->pAttachments[i].srcAlphaBlendFactor, true);
|
||||
out->BlendState.RenderTarget[i].DestBlendAlpha =
|
||||
desc->RenderTarget[i].DestBlendAlpha =
|
||||
translate_blend_factor(in_blend->pAttachments[i].dstAlphaBlendFactor, true);
|
||||
out->BlendState.RenderTarget[i].BlendOpAlpha =
|
||||
desc->RenderTarget[i].BlendOpAlpha =
|
||||
translate_blend_op(in_blend->pAttachments[i].alphaBlendOp);
|
||||
}
|
||||
}
|
||||
|
|
@ -940,15 +1028,17 @@ dzn_graphics_pipeline_create(struct dzn_device *device,
|
|||
if (!pipeline)
|
||||
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
|
||||
|
||||
uintptr_t state_buf[MAX_GFX_PIPELINE_STATE_STREAM_SIZE / sizeof(uintptr_t)];
|
||||
D3D12_PIPELINE_STATE_STREAM_DESC stream_desc = {
|
||||
.pPipelineStateSubobjectStream = state_buf,
|
||||
};
|
||||
|
||||
dzn_pipeline_init(&pipeline->base, device,
|
||||
VK_PIPELINE_BIND_POINT_GRAPHICS,
|
||||
layout);
|
||||
D3D12_INPUT_ELEMENT_DESC attribs[MAX_VERTEX_GENERIC_ATTRIBS] = { 0 };
|
||||
D3D12_INPUT_ELEMENT_DESC inputs[D3D12_VS_INPUT_REGISTER_COUNT] = { 0 };
|
||||
D3D12_GRAPHICS_PIPELINE_STATE_DESC desc = {
|
||||
.pRootSignature = pipeline->base.root.sig,
|
||||
.Flags = D3D12_PIPELINE_STATE_FLAG_NONE,
|
||||
};
|
||||
D3D12_SHADER_BYTECODE *shaders[MESA_VULKAN_SHADER_STAGES] = { 0 };
|
||||
|
||||
const VkPipelineViewportStateCreateInfo *vp_info =
|
||||
pCreateInfo->pRasterizationState->rasterizerDiscardEnable ?
|
||||
|
|
@ -984,11 +1074,11 @@ dzn_graphics_pipeline_create(struct dzn_device *device,
|
|||
}
|
||||
}
|
||||
|
||||
dzn_graphics_pipeline_translate_ia(pipeline, &desc, pCreateInfo);
|
||||
dzn_graphics_pipeline_translate_rast(pipeline, &desc, pCreateInfo);
|
||||
dzn_graphics_pipeline_translate_ms(pipeline, &desc, pCreateInfo);
|
||||
dzn_graphics_pipeline_translate_zsa(pipeline, &desc, pCreateInfo);
|
||||
dzn_graphics_pipeline_translate_blend(pipeline, &desc, pCreateInfo);
|
||||
dzn_graphics_pipeline_translate_ia(pipeline, &stream_desc, pCreateInfo);
|
||||
dzn_graphics_pipeline_translate_rast(pipeline, &stream_desc, pCreateInfo);
|
||||
dzn_graphics_pipeline_translate_ms(pipeline, &stream_desc, pCreateInfo);
|
||||
dzn_graphics_pipeline_translate_zsa(pipeline, &stream_desc, pCreateInfo);
|
||||
dzn_graphics_pipeline_translate_blend(pipeline, &stream_desc, pCreateInfo);
|
||||
|
||||
if (pass) {
|
||||
const struct vk_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
|
||||
|
|
@ -1021,31 +1111,39 @@ dzn_graphics_pipeline_create(struct dzn_device *device,
|
|||
zs_fmt = ri->stencilAttachmentFormat;
|
||||
}
|
||||
|
||||
desc.NumRenderTargets = color_count;
|
||||
for (uint32_t i = 0; i < color_count; i++) {
|
||||
desc.RTVFormats[i] =
|
||||
dzn_image_get_dxgi_format(color_fmts[i],
|
||||
VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
|
||||
VK_IMAGE_ASPECT_COLOR_BIT);
|
||||
if (color_count > 0) {
|
||||
d3d12_gfx_pipeline_state_stream_new_desc(&stream_desc, RENDER_TARGET_FORMATS, struct D3D12_RT_FORMAT_ARRAY, rts);
|
||||
rts->NumRenderTargets = color_count;
|
||||
for (uint32_t i = 0; i < color_count; i++) {
|
||||
rts->RTFormats[i] =
|
||||
dzn_image_get_dxgi_format(color_fmts[i],
|
||||
VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
|
||||
VK_IMAGE_ASPECT_COLOR_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
if (zs_fmt != VK_FORMAT_UNDEFINED) {
|
||||
desc.DSVFormat =
|
||||
d3d12_gfx_pipeline_state_stream_new_desc(&stream_desc, DEPTH_STENCIL_FORMAT, DXGI_FORMAT, ds_fmt);
|
||||
*ds_fmt =
|
||||
dzn_image_get_dxgi_format(zs_fmt,
|
||||
VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT,
|
||||
VK_IMAGE_ASPECT_DEPTH_BIT |
|
||||
VK_IMAGE_ASPECT_STENCIL_BIT);
|
||||
}
|
||||
|
||||
ret = dzn_graphics_pipeline_compile_shaders(device, pipeline, layout, &desc,
|
||||
attribs, inputs,
|
||||
ret = dzn_graphics_pipeline_compile_shaders(device, pipeline, layout,
|
||||
&stream_desc,
|
||||
attribs, inputs, shaders,
|
||||
pCreateInfo);
|
||||
if (ret != VK_SUCCESS)
|
||||
goto out;
|
||||
|
||||
hres = ID3D12Device1_CreateGraphicsPipelineState(device->dev, &desc,
|
||||
&IID_ID3D12PipelineState,
|
||||
(void **)&pipeline->base.state);
|
||||
d3d12_gfx_pipeline_state_stream_new_desc(&stream_desc, ROOT_SIGNATURE, ID3D12RootSignature*, root_sig);
|
||||
*root_sig = pipeline->base.root.sig;
|
||||
|
||||
hres = ID3D12Device2_CreatePipelineState(device->dev, &stream_desc,
|
||||
&IID_ID3D12PipelineState,
|
||||
(void **)&pipeline->base.state);
|
||||
if (FAILED(hres)) {
|
||||
ret = vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
|
||||
goto out;
|
||||
|
|
@ -1054,11 +1152,10 @@ dzn_graphics_pipeline_create(struct dzn_device *device,
|
|||
ret = VK_SUCCESS;
|
||||
|
||||
out:
|
||||
free((void *)desc.VS.pShaderBytecode);
|
||||
free((void *)desc.DS.pShaderBytecode);
|
||||
free((void *)desc.HS.pShaderBytecode);
|
||||
free((void *)desc.GS.pShaderBytecode);
|
||||
free((void *)desc.PS.pShaderBytecode);
|
||||
for (uint32_t i = 0; i < ARRAY_SIZE(shaders); i++) {
|
||||
if (shaders[i])
|
||||
free((void *)shaders[i]->pShaderBytecode);
|
||||
}
|
||||
|
||||
if (ret != VK_SUCCESS)
|
||||
dzn_graphics_pipeline_destroy(pipeline, pAllocator);
|
||||
|
|
@ -1213,11 +1310,15 @@ dzn_compute_pipeline_create(struct dzn_device *device,
|
|||
VK_PIPELINE_BIND_POINT_COMPUTE,
|
||||
layout);
|
||||
|
||||
D3D12_COMPUTE_PIPELINE_STATE_DESC desc = {
|
||||
.pRootSignature = pipeline->base.root.sig,
|
||||
.Flags = D3D12_PIPELINE_STATE_FLAG_NONE,
|
||||
uintptr_t state_buf[MAX_COMPUTE_PIPELINE_STATE_STREAM_SIZE / sizeof(uintptr_t)];
|
||||
D3D12_PIPELINE_STATE_STREAM_DESC stream_desc = {
|
||||
.pPipelineStateSubobjectStream = state_buf,
|
||||
};
|
||||
|
||||
d3d12_gfx_pipeline_state_stream_new_desc(&stream_desc, CS, D3D12_SHADER_BYTECODE, shader);
|
||||
d3d12_gfx_pipeline_state_stream_new_desc(&stream_desc, ROOT_SIGNATURE, ID3D12RootSignature *, root_sig);
|
||||
*root_sig = pipeline->base.root.sig;
|
||||
|
||||
nir_shader *nir = NULL;
|
||||
VkResult ret =
|
||||
dzn_pipeline_get_nir_shader(device, layout,
|
||||
|
|
@ -1228,20 +1329,21 @@ dzn_compute_pipeline_create(struct dzn_device *device,
|
|||
if (ret != VK_SUCCESS)
|
||||
goto out;
|
||||
|
||||
ret = dzn_pipeline_compile_shader(device, nir, &desc.CS);
|
||||
ret = dzn_pipeline_compile_shader(device, nir, shader);
|
||||
if (ret != VK_SUCCESS)
|
||||
goto out;
|
||||
|
||||
if (FAILED(ID3D12Device1_CreateComputePipelineState(device->dev, &desc,
|
||||
&IID_ID3D12PipelineState,
|
||||
(void **)&pipeline->base.state))) {
|
||||
|
||||
if (FAILED(ID3D12Device2_CreatePipelineState(device->dev, &stream_desc,
|
||||
&IID_ID3D12PipelineState,
|
||||
(void **)&pipeline->base.state))) {
|
||||
ret = vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
ralloc_free(nir);
|
||||
free((void *)desc.CS.pShaderBytecode);
|
||||
free((void *)shader->pShaderBytecode);
|
||||
if (ret != VK_SUCCESS)
|
||||
dzn_compute_pipeline_destroy(pipeline, pAllocator);
|
||||
else
|
||||
|
|
|
|||
Loading…
Reference in New Issue