intel/fs: Implement nir_intrinsic_{load,store}_ssbo_block_intel
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7448>
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@ -4003,7 +4003,10 @@ fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr)
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nir_intrinsic_instr *instr)
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{
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{
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/* SSBO stores are weird in that their index is in src[1] */
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/* SSBO stores are weird in that their index is in src[1] */
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const unsigned src = instr->intrinsic == nir_intrinsic_store_ssbo ? 1 : 0;
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const bool is_store =
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instr->intrinsic == nir_intrinsic_store_ssbo ||
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instr->intrinsic == nir_intrinsic_store_ssbo_block_intel;
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const unsigned src = is_store ? 1 : 0;
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if (nir_src_is_const(instr->src[src])) {
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if (nir_src_is_const(instr->src[src])) {
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unsigned index = stage_prog_data->binding_table.ssbo_start +
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unsigned index = stage_prog_data->binding_table.ssbo_start +
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@ -5421,6 +5424,80 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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break;
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break;
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}
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}
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case nir_intrinsic_load_ssbo_block_intel: {
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assert(nir_dest_bit_size(instr->dest) == 32);
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fs_reg address = bld.emit_uniformize(get_nir_src(instr->src[1]));
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fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
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srcs[SURFACE_LOGICAL_SRC_SURFACE] = get_nir_ssbo_intrinsic_index(bld, instr);
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] = address;
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const fs_builder ubld1 = bld.exec_all().group(1, 0);
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const fs_builder ubld8 = bld.exec_all().group(8, 0);
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const fs_builder ubld16 = bld.exec_all().group(16, 0);
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const unsigned total = instr->num_components * dispatch_width;
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unsigned loaded = 0;
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while (loaded < total) {
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const unsigned block =
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choose_oword_block_size_dwords(total - loaded);
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const unsigned block_bytes = block * 4;
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(block);
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const fs_builder &ubld = block == 8 ? ubld8 : ubld16;
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ubld.emit(SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL,
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retype(byte_offset(dest, loaded * 4), BRW_REGISTER_TYPE_UD),
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srcs, SURFACE_LOGICAL_NUM_SRCS)->size_written = block_bytes;
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ubld1.ADD(address, address, brw_imm_ud(block_bytes));
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loaded += block;
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}
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assert(loaded == total);
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break;
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}
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case nir_intrinsic_store_ssbo_block_intel: {
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assert(nir_src_bit_size(instr->src[0]) == 32);
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fs_reg address = bld.emit_uniformize(get_nir_src(instr->src[2]));
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fs_reg src = get_nir_src(instr->src[0]);
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fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
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srcs[SURFACE_LOGICAL_SRC_SURFACE] = get_nir_ssbo_intrinsic_index(bld, instr);
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] = address;
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const fs_builder ubld1 = bld.exec_all().group(1, 0);
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const fs_builder ubld8 = bld.exec_all().group(8, 0);
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const fs_builder ubld16 = bld.exec_all().group(16, 0);
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const unsigned total = instr->num_components * dispatch_width;
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unsigned written = 0;
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while (written < total) {
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const unsigned block =
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choose_oword_block_size_dwords(total - written);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(block);
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srcs[SURFACE_LOGICAL_SRC_DATA] =
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retype(byte_offset(src, written * 4), BRW_REGISTER_TYPE_UD);
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const fs_builder &ubld = block == 8 ? ubld8 : ubld16;
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ubld.emit(SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL,
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fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
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const unsigned block_bytes = block * 4;
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ubld1.ADD(address, address, brw_imm_ud(block_bytes));
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written += block;
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}
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assert(written == total);
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break;
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}
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default:
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default:
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unreachable("unknown intrinsic");
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unreachable("unknown intrinsic");
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}
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}
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