nv50/ir: fix scope of memory ops on ampere
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Karol Herbst <kherbst@redhat.com> Acked-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16784>
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@ -902,8 +902,12 @@ CodeEmitterGV100::emitATOM()
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}
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}
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emitPRED (81);
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emitPRED (81);
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emitField(79, 2, 2); // .INVALID0/./.STRONG/.INVALID3
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if (targ->getChipset() < 0x170) {
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emitField(77, 2, 3); // .CTA/.SM/.GPU/.SYS
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emitField(79, 2, 2); // .INVALID0/./.STRONG/.INVALID3
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emitField(77, 2, 3); // .CTA/.SM/.GPU/.SYS
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} else {
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emitField(77, 4, 0xa); // .STRONG.SYS
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}
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emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
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emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
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emitGPR (32, insn->src(1));
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emitGPR (32, insn->src(1));
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emitADDR (24, 40, 24, 0, insn->src(0));
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emitADDR (24, 40, 24, 0, insn->src(0));
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@ -1036,18 +1040,23 @@ CodeEmitterGV100::emitLDSTc(int posm, int poso)
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{
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{
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int mode = 0;
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int mode = 0;
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int order = 1;
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int order = 1;
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int sm80 = 0;
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switch (insn->cache) {
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switch (insn->cache) {
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case CACHE_CA: mode = 0; order = 1; break;
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case CACHE_CA: mode = 0; order = 1; sm80 = 0x0; break; // .CTA
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case CACHE_CG: mode = 2; order = 2; break;
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case CACHE_CG: mode = 2; order = 2; sm80 = 0x7; break; // .STRONG.GPU
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case CACHE_CV: mode = 3; order = 2; break;
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case CACHE_CV: mode = 3; order = 2; sm80 = 0xa; break; // .STRONG.SYS
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default:
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default:
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assert(!"invalid caching mode");
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assert(!"invalid caching mode");
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break;
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break;
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}
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}
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emitField(poso, 2, order);
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if (targ->getChipset() < 0x170) {
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emitField(posm, 2, mode);
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emitField(poso, 2, order);
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emitField(posm, 2, mode);
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} else {
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emitField(posm, 4, sm80);
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}
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}
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}
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void
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void
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@ -1073,8 +1082,12 @@ void
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CodeEmitterGV100::emitLD()
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CodeEmitterGV100::emitLD()
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{
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{
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emitInsn (0x980);
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emitInsn (0x980);
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emitField(79, 2, 2); // .CONSTANT/./.STRONG/.MMIO
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if (targ->getChipset() < 0x170) {
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emitField(77, 2, 2); // .CTA/.SM/.GPU/.SYS
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emitField(79, 2, 2); // .CONSTANT/./.STRONG/.MMIO
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emitField(77, 2, 2); // .CTA/.SM/.GPU/.SYS
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} else {
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emitField(77, 4, 0x7); // .STRONG.GPU
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}
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emitLDSTs(73, insn->dType);
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emitLDSTs(73, insn->dType);
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emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
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emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
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emitADDR (24, 32, 32, 0, insn->src(0));
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emitADDR (24, 32, 32, 0, insn->src(0));
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@ -1143,8 +1156,12 @@ CodeEmitterGV100::emitRED()
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emitInsn (0x98e);
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emitInsn (0x98e);
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emitField(87, 3, insn->subOp);
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emitField(87, 3, insn->subOp);
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emitField(84, 3, 1); // 0=.EF, 1=, 2=.EL, 3=.LU, 4=.EU, 5=.NA
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emitField(84, 3, 1); // 0=.EF, 1=, 2=.EL, 3=.LU, 4=.EU, 5=.NA
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emitField(79, 2, 2); // .INVALID0/./.STRONG/.INVALID3
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if (targ->getChipset() < 0x170) {
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emitField(77, 2, 3); // .CTA/.SM/.GPU/.SYS
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emitField(79, 2, 2); // .INVALID0/./.STRONG/.INVALID3
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emitField(77, 2, 3); // .CTA/.SM/.GPU/.SYS
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} else {
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emitField(77, 4, 0xa); // .STRONG.SYS
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}
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emitField(73, 3, dType);
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emitField(73, 3, dType);
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emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
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emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
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emitGPR (32, insn->src(1));
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emitGPR (32, insn->src(1));
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@ -1155,8 +1172,12 @@ void
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CodeEmitterGV100::emitST()
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CodeEmitterGV100::emitST()
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{
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{
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emitInsn (0x385);
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emitInsn (0x385);
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emitField(79, 2, 2); // .INVALID0/./.STRONG/.MMIO
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if (targ->getChipset() < 0x170) {
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emitField(77, 2, 2); // .CTA/.SM/.GPU/.SYS
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emitField(79, 2, 2); // .INVALID0/./.STRONG/.MMIO
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emitField(77, 2, 2); // .CTA/.SM/.GPU/.SYS
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} else {
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emitField(77, 4, 0x7); // .STRONG.GPU
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}
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emitLDSTs(73, insn->dType);
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emitLDSTs(73, insn->dType);
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emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
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emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
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emitGPR (64, insn->src(1));
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emitGPR (64, insn->src(1));
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@ -1472,7 +1493,8 @@ CodeEmitterGV100::emitSUATOM()
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emitField(87, 4, subOp);
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emitField(87, 4, subOp);
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emitPRED (81);
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emitPRED (81);
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emitField(79, 2, 1);
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if (targ->getChipset() < 0x170)
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emitField(79, 2, 1);
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emitField(73, 3, type);
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emitField(73, 3, type);
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emitField(72, 1, 0); // .BA
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emitField(72, 1, 0); // .BA
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emitGPR (32, insn->src(1));
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emitGPR (32, insn->src(1));
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