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nv50/ir: fix scope of memory ops on ampere 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16784>
This commit is contained in:
Ben Skeggs 2021-11-06 09:51:59 +10:00 committed by Marge Bot
parent ca04eff600
commit 9fd1602fb5
1 changed files with 36 additions and 14 deletions
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50
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.cpp
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@ -902,8 +902,12 @@ CodeEmitterGV100::emitATOM()
}
emitPRED (81);
emitField(79, 2, 2); // .INVALID0/./.STRONG/.INVALID3
emitField(77, 2, 3); // .CTA/.SM/.GPU/.SYS
if (targ->getChipset() < 0x170) {
emitField(79, 2, 2); // .INVALID0/./.STRONG/.INVALID3
emitField(77, 2, 3); // .CTA/.SM/.GPU/.SYS
} else {
emitField(77, 4, 0xa); // .STRONG.SYS
}
emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
emitGPR (32, insn->src(1));
emitADDR (24, 40, 24, 0, insn->src(0));
@ -1036,18 +1040,23 @@ CodeEmitterGV100::emitLDSTc(int posm, int poso)
{
int mode = 0;
int order = 1;
int sm80 = 0;
switch (insn->cache) {
case CACHE_CA: mode = 0; order = 1; break;
case CACHE_CG: mode = 2; order = 2; break;
case CACHE_CV: mode = 3; order = 2; break;
case CACHE_CA: mode = 0; order = 1; sm80 = 0x0; break; // .CTA
case CACHE_CG: mode = 2; order = 2; sm80 = 0x7; break; // .STRONG.GPU
case CACHE_CV: mode = 3; order = 2; sm80 = 0xa; break; // .STRONG.SYS
default:
assert(!"invalid caching mode");
break;
}
emitField(poso, 2, order);
emitField(posm, 2, mode);
if (targ->getChipset() < 0x170) {
emitField(poso, 2, order);
emitField(posm, 2, mode);
} else {
emitField(posm, 4, sm80);
}
}
void
@ -1073,8 +1082,12 @@ void
CodeEmitterGV100::emitLD()
{
emitInsn (0x980);
emitField(79, 2, 2); // .CONSTANT/./.STRONG/.MMIO
emitField(77, 2, 2); // .CTA/.SM/.GPU/.SYS
if (targ->getChipset() < 0x170) {
emitField(79, 2, 2); // .CONSTANT/./.STRONG/.MMIO
emitField(77, 2, 2); // .CTA/.SM/.GPU/.SYS
} else {
emitField(77, 4, 0x7); // .STRONG.GPU
}
emitLDSTs(73, insn->dType);
emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
emitADDR (24, 32, 32, 0, insn->src(0));
@ -1143,8 +1156,12 @@ CodeEmitterGV100::emitRED()
emitInsn (0x98e);
emitField(87, 3, insn->subOp);
emitField(84, 3, 1); // 0=.EF, 1=, 2=.EL, 3=.LU, 4=.EU, 5=.NA
emitField(79, 2, 2); // .INVALID0/./.STRONG/.INVALID3
emitField(77, 2, 3); // .CTA/.SM/.GPU/.SYS
if (targ->getChipset() < 0x170) {
emitField(79, 2, 2); // .INVALID0/./.STRONG/.INVALID3
emitField(77, 2, 3); // .CTA/.SM/.GPU/.SYS
} else {
emitField(77, 4, 0xa); // .STRONG.SYS
}
emitField(73, 3, dType);
emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
emitGPR (32, insn->src(1));
@ -1155,8 +1172,12 @@ void
CodeEmitterGV100::emitST()
{
emitInsn (0x385);
emitField(79, 2, 2); // .INVALID0/./.STRONG/.MMIO
emitField(77, 2, 2); // .CTA/.SM/.GPU/.SYS
if (targ->getChipset() < 0x170) {
emitField(79, 2, 2); // .INVALID0/./.STRONG/.MMIO
emitField(77, 2, 2); // .CTA/.SM/.GPU/.SYS
} else {
emitField(77, 4, 0x7); // .STRONG.GPU
}
emitLDSTs(73, insn->dType);
emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
emitGPR (64, insn->src(1));
@ -1472,7 +1493,8 @@ CodeEmitterGV100::emitSUATOM()
emitField(87, 4, subOp);
emitPRED (81);
emitField(79, 2, 1);
if (targ->getChipset() < 0x170)
emitField(79, 2, 1);
emitField(73, 3, type);
emitField(72, 1, 0); // .BA
emitGPR (32, insn->src(1));