i965: Make intelEmitCopyBlit static
And rename to emit_copy_blit. v2: sed --in-place -e 's/color_logic_ops/gl_logicop_mode/g' $(grep -lr color_logic_ops src/) suggested by Brian. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> [v1]
This commit is contained in:
Ian Romanick
parent
4e9e964de6
commit
9eed6bea6b
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@ -202,6 +202,183 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
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}
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}
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static bool
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alignment_valid(struct brw_context *brw, unsigned offset,
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enum isl_tiling tiling)
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{
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const struct gen_device_info *devinfo = &brw->screen->devinfo;
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/* Tiled buffers must be page-aligned (4K). */
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if (tiling != ISL_TILING_LINEAR)
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return (offset & 4095) == 0;
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/* On Gen8+, linear buffers must be cacheline-aligned. */
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if (devinfo->gen >= 8)
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return (offset & 63) == 0;
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return true;
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}
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static uint32_t
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xy_blit_cmd(enum isl_tiling src_tiling, enum isl_tiling dst_tiling,
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uint32_t cpp)
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{
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uint32_t CMD = 0;
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assert(cpp <= 4);
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switch (cpp) {
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case 1:
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case 2:
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CMD = XY_SRC_COPY_BLT_CMD;
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break;
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case 4:
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CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
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break;
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default:
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unreachable("not reached");
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}
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if (dst_tiling != ISL_TILING_LINEAR)
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CMD |= XY_DST_TILED;
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if (src_tiling != ISL_TILING_LINEAR)
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CMD |= XY_SRC_TILED;
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return CMD;
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}
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/* Copy BitBlt
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*/
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static bool
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emit_copy_blit(struct brw_context *brw,
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GLuint cpp,
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int32_t src_pitch,
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struct brw_bo *src_buffer,
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GLuint src_offset,
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enum isl_tiling src_tiling,
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int32_t dst_pitch,
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struct brw_bo *dst_buffer,
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GLuint dst_offset,
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enum isl_tiling dst_tiling,
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GLshort src_x, GLshort src_y,
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GLshort dst_x, GLshort dst_y,
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GLshort w, GLshort h,
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enum gl_logicop_mode logic_op)
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{
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const struct gen_device_info *devinfo = &brw->screen->devinfo;
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GLuint CMD, BR13;
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int dst_y2 = dst_y + h;
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int dst_x2 = dst_x + w;
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bool dst_y_tiled = dst_tiling == ISL_TILING_Y0;
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bool src_y_tiled = src_tiling == ISL_TILING_Y0;
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uint32_t src_tile_w, src_tile_h;
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uint32_t dst_tile_w, dst_tile_h;
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if ((dst_y_tiled || src_y_tiled) && devinfo->gen < 6)
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return false;
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const unsigned bo_sizes = dst_buffer->size + src_buffer->size;
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/* do space check before going any further */
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if (!brw_batch_has_aperture_space(brw, bo_sizes))
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intel_batchbuffer_flush(brw);
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if (!brw_batch_has_aperture_space(brw, bo_sizes))
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return false;
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unsigned length = devinfo->gen >= 8 ? 10 : 8;
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intel_batchbuffer_require_space(brw, length * 4, BLT_RING);
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DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
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__func__,
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src_buffer, src_pitch, src_offset, src_x, src_y,
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dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
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intel_get_tile_dims(src_tiling, cpp, &src_tile_w, &src_tile_h);
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intel_get_tile_dims(dst_tiling, cpp, &dst_tile_w, &dst_tile_h);
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/* For Tiled surfaces, the pitch has to be a multiple of the Tile width
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* (X direction width of the Tile). This is ensured while allocating the
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* buffer object.
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*/
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assert(src_tiling == ISL_TILING_LINEAR || (src_pitch % src_tile_w) == 0);
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assert(dst_tiling == ISL_TILING_LINEAR || (dst_pitch % dst_tile_w) == 0);
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/* For big formats (such as floating point), do the copy using 16 or
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* 32bpp and multiply the coordinates.
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*/
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if (cpp > 4) {
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if (cpp % 4 == 2) {
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dst_x *= cpp / 2;
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dst_x2 *= cpp / 2;
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src_x *= cpp / 2;
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cpp = 2;
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} else {
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assert(cpp % 4 == 0);
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dst_x *= cpp / 4;
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dst_x2 *= cpp / 4;
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src_x *= cpp / 4;
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cpp = 4;
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}
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}
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if (!alignment_valid(brw, dst_offset, dst_tiling))
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return false;
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if (!alignment_valid(brw, src_offset, src_tiling))
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return false;
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/* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
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* the low bits. Offsets must be naturally aligned.
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*/
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if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
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dst_pitch % 4 != 0 || dst_offset % cpp != 0)
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return false;
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assert(cpp <= 4);
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BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
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CMD = xy_blit_cmd(src_tiling, dst_tiling, cpp);
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/* For tiled source and destination, pitch value should be specified
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* as a number of Dwords.
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*/
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if (dst_tiling != ISL_TILING_LINEAR)
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dst_pitch /= 4;
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if (src_tiling != ISL_TILING_LINEAR)
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src_pitch /= 4;
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if (dst_y2 <= dst_y || dst_x2 <= dst_x)
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return true;
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assert(dst_x < dst_x2);
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assert(dst_y < dst_y2);
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BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
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OUT_BATCH(CMD | (length - 2));
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OUT_BATCH(BR13 | (uint16_t)dst_pitch);
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OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
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OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
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if (devinfo->gen >= 8) {
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OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset);
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} else {
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OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset);
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}
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OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
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OUT_BATCH((uint16_t)src_pitch);
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if (devinfo->gen >= 8) {
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OUT_RELOC64(src_buffer, 0, src_offset);
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} else {
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OUT_RELOC(src_buffer, 0, src_offset);
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}
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ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
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brw_emit_mi_flush(brw);
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return true;
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}
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static bool
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emit_miptree_blit(struct brw_context *brw,
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struct intel_mipmap_tree *src_mt,
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@ -254,19 +431,19 @@ emit_miptree_blit(struct brw_context *brw,
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dst_x + chunk_x, dst_y + chunk_y,
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&dst_offset, &dst_tile_x, &dst_tile_y);
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if (!intelEmitCopyBlit(brw,
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src_mt->cpp,
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reverse ? -src_mt->surf.row_pitch :
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src_mt->surf.row_pitch,
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src_mt->bo, src_mt->offset + src_offset,
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src_mt->surf.tiling,
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dst_mt->surf.row_pitch,
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dst_mt->bo, dst_mt->offset + dst_offset,
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dst_mt->surf.tiling,
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src_tile_x, src_tile_y,
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dst_tile_x, dst_tile_y,
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chunk_w, chunk_h,
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logicop)) {
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if (!emit_copy_blit(brw,
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src_mt->cpp,
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reverse ? -src_mt->surf.row_pitch :
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src_mt->surf.row_pitch,
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src_mt->bo, src_mt->offset + src_offset,
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src_mt->surf.tiling,
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dst_mt->surf.row_pitch,
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dst_mt->bo, dst_mt->offset + dst_offset,
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dst_mt->surf.tiling,
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src_tile_x, src_tile_y,
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dst_tile_x, dst_tile_y,
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chunk_w, chunk_h,
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logicop)) {
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/* If this is ever going to fail, it will fail on the first chunk */
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assert(chunk_x == 0 && chunk_y == 0);
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return false;
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@ -448,183 +625,6 @@ intel_miptree_copy(struct brw_context *brw,
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src_width, src_height, false, COLOR_LOGICOP_COPY);
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}
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static bool
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alignment_valid(struct brw_context *brw, unsigned offset,
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enum isl_tiling tiling)
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{
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const struct gen_device_info *devinfo = &brw->screen->devinfo;
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/* Tiled buffers must be page-aligned (4K). */
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if (tiling != ISL_TILING_LINEAR)
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return (offset & 4095) == 0;
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/* On Gen8+, linear buffers must be cacheline-aligned. */
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if (devinfo->gen >= 8)
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return (offset & 63) == 0;
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return true;
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}
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static uint32_t
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xy_blit_cmd(enum isl_tiling src_tiling, enum isl_tiling dst_tiling,
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uint32_t cpp)
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{
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uint32_t CMD = 0;
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assert(cpp <= 4);
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switch (cpp) {
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case 1:
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case 2:
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CMD = XY_SRC_COPY_BLT_CMD;
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break;
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case 4:
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CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
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break;
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default:
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unreachable("not reached");
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}
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if (dst_tiling != ISL_TILING_LINEAR)
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CMD |= XY_DST_TILED;
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if (src_tiling != ISL_TILING_LINEAR)
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CMD |= XY_SRC_TILED;
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return CMD;
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}
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/* Copy BitBlt
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*/
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bool
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intelEmitCopyBlit(struct brw_context *brw,
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GLuint cpp,
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int32_t src_pitch,
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struct brw_bo *src_buffer,
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GLuint src_offset,
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enum isl_tiling src_tiling,
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int32_t dst_pitch,
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struct brw_bo *dst_buffer,
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GLuint dst_offset,
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enum isl_tiling dst_tiling,
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GLshort src_x, GLshort src_y,
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GLshort dst_x, GLshort dst_y,
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GLshort w, GLshort h,
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enum gl_logicop_mode logic_op)
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{
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const struct gen_device_info *devinfo = &brw->screen->devinfo;
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GLuint CMD, BR13;
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int dst_y2 = dst_y + h;
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int dst_x2 = dst_x + w;
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bool dst_y_tiled = dst_tiling == ISL_TILING_Y0;
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bool src_y_tiled = src_tiling == ISL_TILING_Y0;
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uint32_t src_tile_w, src_tile_h;
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uint32_t dst_tile_w, dst_tile_h;
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if ((dst_y_tiled || src_y_tiled) && devinfo->gen < 6)
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return false;
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const unsigned bo_sizes = dst_buffer->size + src_buffer->size;
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/* do space check before going any further */
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if (!brw_batch_has_aperture_space(brw, bo_sizes))
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intel_batchbuffer_flush(brw);
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if (!brw_batch_has_aperture_space(brw, bo_sizes))
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return false;
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unsigned length = devinfo->gen >= 8 ? 10 : 8;
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intel_batchbuffer_require_space(brw, length * 4, BLT_RING);
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DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
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__func__,
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src_buffer, src_pitch, src_offset, src_x, src_y,
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dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
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intel_get_tile_dims(src_tiling, cpp, &src_tile_w, &src_tile_h);
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intel_get_tile_dims(dst_tiling, cpp, &dst_tile_w, &dst_tile_h);
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/* For Tiled surfaces, the pitch has to be a multiple of the Tile width
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* (X direction width of the Tile). This is ensured while allocating the
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* buffer object.
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*/
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assert(src_tiling == ISL_TILING_LINEAR || (src_pitch % src_tile_w) == 0);
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assert(dst_tiling == ISL_TILING_LINEAR || (dst_pitch % dst_tile_w) == 0);
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/* For big formats (such as floating point), do the copy using 16 or
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* 32bpp and multiply the coordinates.
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*/
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if (cpp > 4) {
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if (cpp % 4 == 2) {
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dst_x *= cpp / 2;
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dst_x2 *= cpp / 2;
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src_x *= cpp / 2;
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cpp = 2;
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} else {
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assert(cpp % 4 == 0);
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dst_x *= cpp / 4;
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dst_x2 *= cpp / 4;
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src_x *= cpp / 4;
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cpp = 4;
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}
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}
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if (!alignment_valid(brw, dst_offset, dst_tiling))
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return false;
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if (!alignment_valid(brw, src_offset, src_tiling))
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return false;
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/* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
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* the low bits. Offsets must be naturally aligned.
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*/
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if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
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dst_pitch % 4 != 0 || dst_offset % cpp != 0)
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return false;
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assert(cpp <= 4);
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BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
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CMD = xy_blit_cmd(src_tiling, dst_tiling, cpp);
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/* For tiled source and destination, pitch value should be specified
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* as a number of Dwords.
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*/
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if (dst_tiling != ISL_TILING_LINEAR)
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dst_pitch /= 4;
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if (src_tiling != ISL_TILING_LINEAR)
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src_pitch /= 4;
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if (dst_y2 <= dst_y || dst_x2 <= dst_x)
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return true;
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assert(dst_x < dst_x2);
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assert(dst_y < dst_y2);
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BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
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OUT_BATCH(CMD | (length - 2));
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OUT_BATCH(BR13 | (uint16_t)dst_pitch);
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OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
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OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
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if (devinfo->gen >= 8) {
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OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset);
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} else {
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OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset);
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}
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OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
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OUT_BATCH((uint16_t)src_pitch);
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if (devinfo->gen >= 8) {
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OUT_RELOC64(src_buffer, 0, src_offset);
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} else {
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OUT_RELOC(src_buffer, 0, src_offset);
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}
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ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
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brw_emit_mi_flush(brw);
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return true;
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}
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bool
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intelEmitImmediateColorExpandBlit(struct brw_context *brw,
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GLuint cpp,
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@ -737,15 +737,15 @@ intel_emit_linear_blit(struct brw_context *brw,
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assert(src_x + pitch < 1 << 15);
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assert(dst_x + pitch < 1 << 15);
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ok = intelEmitCopyBlit(brw, 1,
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pitch, src_bo, src_offset - src_x,
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ISL_TILING_LINEAR,
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pitch, dst_bo, dst_offset - dst_x,
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ISL_TILING_LINEAR,
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src_x, 0, /* src x/y */
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dst_x, 0, /* dst x/y */
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MIN2(size, pitch), height, /* w, h */
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COLOR_LOGICOP_COPY);
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ok = emit_copy_blit(brw, 1,
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pitch, src_bo, src_offset - src_x,
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ISL_TILING_LINEAR,
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pitch, dst_bo, dst_offset - dst_x,
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ISL_TILING_LINEAR,
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src_x, 0, /* src x/y */
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dst_x, 0, /* dst x/y */
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MIN2(size, pitch), height, /* w, h */
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COLOR_LOGICOP_COPY);
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if (!ok) {
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_mesa_problem(ctx, "Failed to linear blit %dx%d\n",
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MIN2(size, pitch), height);
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@ -28,22 +28,6 @@
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#include "brw_context.h"
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bool
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intelEmitCopyBlit(struct brw_context *brw,
|
||||
GLuint cpp,
|
||||
int32_t src_pitch,
|
||||
struct brw_bo *src_buffer,
|
||||
GLuint src_offset,
|
||||
enum isl_tiling src_tiling,
|
||||
int32_t dst_pitch,
|
||||
struct brw_bo *dst_buffer,
|
||||
GLuint dst_offset,
|
||||
enum isl_tiling dst_tiling,
|
||||
GLshort srcx, GLshort srcy,
|
||||
GLshort dstx, GLshort dsty,
|
||||
GLshort w, GLshort h,
|
||||
enum gl_logicop_mode logicop);
|
||||
|
||||
bool intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst);
|
||||
|
||||
bool intel_miptree_blit(struct brw_context *brw,
|
||||
|
|
|
|||
Loading…
Reference in New Issue