i965: Move intel_miptree_choose_tiling() to brw_tex_layout.c
and change the name to brw_miptree_choose_tiling(). V3: Remove redundant function parameters. (Topi) Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Anuj Phogat
parent
2cbe730ac5
commit
9edac38f2a
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@ -458,6 +458,108 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
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align_cube(mt);
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}
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/**
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* \brief Helper function for intel_miptree_create().
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*/
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static uint32_t
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brw_miptree_choose_tiling(struct brw_context *brw,
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enum intel_miptree_tiling_mode requested,
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const struct intel_mipmap_tree *mt)
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{
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if (mt->format == MESA_FORMAT_S_UINT8) {
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/* The stencil buffer is W tiled. However, we request from the kernel a
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* non-tiled buffer because the GTT is incapable of W fencing.
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*/
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return I915_TILING_NONE;
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}
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/* Some usages may want only one type of tiling, like depth miptrees (Y
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* tiled), or temporary BOs for uploading data once (linear).
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*/
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switch (requested) {
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case INTEL_MIPTREE_TILING_ANY:
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break;
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case INTEL_MIPTREE_TILING_Y:
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return I915_TILING_Y;
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case INTEL_MIPTREE_TILING_NONE:
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return I915_TILING_NONE;
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}
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if (mt->num_samples > 1) {
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/* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
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* Surface"):
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*
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* [DevSNB+]: For multi-sample render targets, this field must be
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* 1. MSRTs can only be tiled.
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*
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* Our usual reason for preferring X tiling (fast blits using the
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* blitting engine) doesn't apply to MSAA, since we'll generally be
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* downsampling or upsampling when blitting between the MSAA buffer
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* and another buffer, and the blitting engine doesn't support that.
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* So use Y tiling, since it makes better use of the cache.
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*/
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return I915_TILING_Y;
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}
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GLenum base_format = _mesa_get_format_base_format(mt->format);
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if (base_format == GL_DEPTH_COMPONENT ||
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base_format == GL_DEPTH_STENCIL_EXT)
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return I915_TILING_Y;
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/* 1D textures (and 1D array textures) don't get any benefit from tiling,
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* in fact it leads to a less efficient use of memory space and bandwidth
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* due to tile alignment.
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*/
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if (mt->logical_height0 == 1)
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return I915_TILING_NONE;
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int minimum_pitch = mt->total_width * mt->cpp;
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/* If the width is much smaller than a tile, don't bother tiling. */
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if (minimum_pitch < 64)
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return I915_TILING_NONE;
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if (ALIGN(minimum_pitch, 512) >= 32768 ||
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mt->total_width >= 32768 || mt->total_height >= 32768) {
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perf_debug("%dx%d miptree too large to blit, falling back to untiled",
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mt->total_width, mt->total_height);
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return I915_TILING_NONE;
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}
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/* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
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if (brw->gen < 6)
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return I915_TILING_X;
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/* From the Sandybridge PRM, Volume 1, Part 2, page 32:
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* "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
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* or Linear."
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* 128 bits per pixel translates to 16 bytes per pixel. This is necessary
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* all the way back to 965, but is permitted on Gen7+.
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*/
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if (brw->gen < 7 && mt->cpp >= 16)
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return I915_TILING_X;
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/* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
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* messages), on p64, under the heading "Surface Vertical Alignment":
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*
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* This field must be set to VALIGN_4 for all tiled Y Render Target
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* surfaces.
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*
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* So if the surface is renderable and uses a vertical alignment of 2,
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* force it to be X tiled. This is somewhat conservative (it's possible
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* that the client won't ever render to this surface), but it's difficult
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* to know that ahead of time. And besides, since we use a vertical
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* alignment of 4 as often as we can, this shouldn't happen very often.
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*/
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if (brw->gen == 7 && mt->align_h == 2 &&
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brw->format_supported_as_render_target[mt->format]) {
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return I915_TILING_X;
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}
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return I915_TILING_Y | I915_TILING_X;
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}
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void
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brw_miptree_layout(struct brw_context *brw,
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bool for_bo,
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@ -562,9 +664,6 @@ brw_miptree_layout(struct brw_context *brw,
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}
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if (!for_bo)
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mt->tiling = intel_miptree_choose_tiling(brw, mt->format,
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mt->logical_width0,
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mt->num_samples,
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requested, mt);
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mt->tiling = brw_miptree_choose_tiling(brw, requested, mt);
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}
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@ -482,110 +482,6 @@ intel_miptree_create_layout(struct brw_context *brw,
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return mt;
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}
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/**
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* \brief Helper function for intel_miptree_create().
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*/
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uint32_t
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intel_miptree_choose_tiling(struct brw_context *brw,
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mesa_format format,
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uint32_t width0,
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uint32_t num_samples,
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enum intel_miptree_tiling_mode requested,
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struct intel_mipmap_tree *mt)
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{
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if (format == MESA_FORMAT_S_UINT8) {
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/* The stencil buffer is W tiled. However, we request from the kernel a
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* non-tiled buffer because the GTT is incapable of W fencing.
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*/
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return I915_TILING_NONE;
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}
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/* Some usages may want only one type of tiling, like depth miptrees (Y
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* tiled), or temporary BOs for uploading data once (linear).
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*/
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switch (requested) {
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case INTEL_MIPTREE_TILING_ANY:
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break;
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case INTEL_MIPTREE_TILING_Y:
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return I915_TILING_Y;
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case INTEL_MIPTREE_TILING_NONE:
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return I915_TILING_NONE;
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}
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if (num_samples > 1) {
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/* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
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* Surface"):
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*
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* [DevSNB+]: For multi-sample render targets, this field must be
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* 1. MSRTs can only be tiled.
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*
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* Our usual reason for preferring X tiling (fast blits using the
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* blitting engine) doesn't apply to MSAA, since we'll generally be
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* downsampling or upsampling when blitting between the MSAA buffer
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* and another buffer, and the blitting engine doesn't support that.
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* So use Y tiling, since it makes better use of the cache.
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*/
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return I915_TILING_Y;
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}
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GLenum base_format = _mesa_get_format_base_format(format);
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if (base_format == GL_DEPTH_COMPONENT ||
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base_format == GL_DEPTH_STENCIL_EXT)
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return I915_TILING_Y;
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/* 1D textures (and 1D array textures) don't get any benefit from tiling,
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* in fact it leads to a less efficient use of memory space and bandwidth
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* due to tile alignment.
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*/
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if (mt->logical_height0 == 1)
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return I915_TILING_NONE;
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int minimum_pitch = mt->total_width * mt->cpp;
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/* If the width is much smaller than a tile, don't bother tiling. */
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if (minimum_pitch < 64)
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return I915_TILING_NONE;
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if (ALIGN(minimum_pitch, 512) >= 32768 ||
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mt->total_width >= 32768 || mt->total_height >= 32768) {
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perf_debug("%dx%d miptree too large to blit, falling back to untiled",
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mt->total_width, mt->total_height);
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return I915_TILING_NONE;
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}
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/* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
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if (brw->gen < 6)
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return I915_TILING_X;
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/* From the Sandybridge PRM, Volume 1, Part 2, page 32:
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* "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
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* or Linear."
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* 128 bits per pixel translates to 16 bytes per pixel. This is necessary
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* all the way back to 965, but is permitted on Gen7+.
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*/
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if (brw->gen < 7 && mt->cpp >= 16)
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return I915_TILING_X;
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/* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
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* messages), on p64, under the heading "Surface Vertical Alignment":
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*
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* This field must be set to VALIGN_4 for all tiled Y Render Target
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* surfaces.
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*
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* So if the surface is renderable and uses a vertical alignment of 2,
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* force it to be X tiled. This is somewhat conservative (it's possible
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* that the client won't ever render to this surface), but it's difficult
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* to know that ahead of time. And besides, since we use a vertical
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* alignment of 4 as often as we can, this shouldn't happen very often.
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*/
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if (brw->gen == 7 && mt->align_h == 2 &&
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brw->format_supported_as_render_target[format]) {
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return I915_TILING_X;
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}
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return I915_TILING_Y | I915_TILING_X;
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}
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/**
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* Choose an appropriate uncompressed format for a requested
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@ -784,14 +784,6 @@ intel_miptree_unmap(struct brw_context *brw,
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unsigned int level,
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unsigned int slice);
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uint32_t
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intel_miptree_choose_tiling(struct brw_context *brw,
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mesa_format format,
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uint32_t width0,
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uint32_t num_samples,
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enum intel_miptree_tiling_mode requested,
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struct intel_mipmap_tree *mt);
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void
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intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
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unsigned int level, unsigned int layer, enum gen6_hiz_op op);
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