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program: Remove OPCODE_KIL_NV. 

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Brian Paul <brianp@vmware.com>
This commit is contained in:
Matt Turner 2016-02-27 13:19:50 -08:00
parent a0c3650ad3
commit 9e11ff7e11
8 changed files with 6 additions and 54 deletions
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20
src/mesa/drivers/dri/i915/i915_fragprog.c
View File

@ -598,26 +598,6 @@ upload_program(struct i915_fragment_program *p)
0, src0, T0_TEXKILL);
break;
case OPCODE_KIL_NV:
if (inst->DstReg.CondMask == COND_TR) {
tmp = i915_get_utemp(p);
/* The KIL instruction discards the fragment if any component of
* the source is < 0. Emit an immediate operand of {-1}.xywz.
*/
i915_emit_texld(p, get_live_regs(p, inst),
tmp, A0_DEST_CHANNEL_ALL,
0, /* use a dummy dest reg */
negate(swizzle(tmp, ONE, ONE, ONE, ONE),
1, 1, 1, 1),
T0_TEXKILL);
} else {
p->error = 1;
i915_program_error(p, "Unsupported KIL_NV condition code: %d",
inst->DstReg.CondMask);
}
break;
case OPCODE_LG2:
src0 = src_vector(p, &inst->SrcReg[0], program);

13
src/mesa/program/ir_to_mesa.cpp
View File

@ -2112,13 +2112,12 @@ ir_to_mesa_visitor::visit(ir_return *ir)
void
ir_to_mesa_visitor::visit(ir_discard *ir)
{
if (ir->condition) {
ir->condition->accept(this);
this->result.negate = ~this->result.negate;
emit(ir, OPCODE_KIL, undef_dst, this->result);
} else {
emit(ir, OPCODE_KIL_NV);
}
if (!ir->condition)
ir->condition = new(mem_ctx) ir_constant(true);
ir->condition->accept(this);
this->result.negate = ~this->result.negate;
emit(ir, OPCODE_KIL, undef_dst, this->result);
}
void

5
src/mesa/program/prog_execute.c
View File

@ -805,11 +805,6 @@ _mesa_execute_program(struct gl_context * ctx,
case OPCODE_ENDIF:
/* nothing */
break;
case OPCODE_KIL_NV: /* NV_f_p only (conditional) */
if (eval_condition(machine, inst)) {
return GL_FALSE;
}
break;
case OPCODE_KIL: /* ARB_f_p only */
{
GLfloat a[4];

1
src/mesa/program/prog_instruction.c
View File

@ -154,7 +154,6 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
{ OPCODE_FRC, "FRC", 1, 1 },
{ OPCODE_IF, "IF", 1, 0 },
{ OPCODE_KIL, "KIL", 1, 0 },
{ OPCODE_KIL_NV, "KIL_NV", 0, 0 },
{ OPCODE_LG2, "LG2", 1, 1 },
{ OPCODE_LIT, "LIT", 1, 1 },
{ OPCODE_LOG, "LOG", 1, 1 },

1
src/mesa/program/prog_instruction.h
View File

@ -166,7 +166,6 @@ enum prog_opcode {
OPCODE_FRC, /* X X 2 X X */
OPCODE_IF, /* opt */
OPCODE_KIL, /* X X */
OPCODE_KIL_NV, /* X X */
OPCODE_LG2, /* X X 2 X X */
OPCODE_LIT, /* X X X X */
OPCODE_LOG, /* X X */

10
src/mesa/program/prog_print.c
View File

@ -706,16 +706,6 @@ _mesa_fprint_instruction_opt(FILE *f,
fprint_src_reg(f, &inst->SrcReg[0], mode, prog);
fprint_comment(f, inst);
break;
case OPCODE_KIL_NV:
fprintf(f, "%s", _mesa_opcode_string(inst->Opcode));
fprintf(f, " ");
fprintf(f, "%s.%s",
_mesa_condcode_string(inst->DstReg.CondMask),
_mesa_swizzle_string(inst->DstReg.CondSwizzle,
GL_FALSE, GL_FALSE));
fprint_comment(f, inst);
break;
case OPCODE_ARL:
fprintf(f, "ARL ");
fprint_dst_reg(f, &inst->DstReg, mode, prog);

7
src/mesa/program/program_parse.y
View File

@ -471,13 +471,6 @@ KIL_instruction: KIL swizzleSrcReg
$$ = asm_instruction_ctor(OPCODE_KIL, NULL, & $2, NULL, NULL);
state->fragment.UsesKill = 1;
}
| KIL ccTest
{
$$ = asm_instruction_ctor(OPCODE_KIL_NV, NULL, NULL, NULL, NULL);
$$->Base.DstReg.CondMask = $2.CondMask;
$$->Base.DstReg.CondSwizzle = $2.CondSwizzle;
state->fragment.UsesKill = 1;
}
;
TXD_instruction: TXD_OP maskedDstReg ',' swizzleSrcReg ',' swizzleSrcReg ',' swizzleSrcReg ',' texImageUnit ',' texTarget

3
src/mesa/state_tracker/st_mesa_to_tgsi.c
View File

@ -526,9 +526,6 @@ translate_opcode( unsigned op )
return TGSI_OPCODE_TRUNC;
case OPCODE_KIL:
return TGSI_OPCODE_KILL_IF;
case OPCODE_KIL_NV:
/* XXX we don't support condition codes in TGSI */
return TGSI_OPCODE_KILL;
case OPCODE_LG2:
return TGSI_OPCODE_LG2;
case OPCODE_LOG: